Test Under Real Conditions (EE Tip #137)

The world’s best engineers have one thing in common: they’re always learning from their mistakes. We asked Niagara College professor and long-time contributor Mark Csele about his biggest engineering-related mistake. He responded with the following interesting insight about testing under real conditions.

Mark Csele's complete portable accelerometer design, which he presented in Circuit Cellar 266.  with the serial download adapter. The adapter is installed only when downloading data to a PC and mates with an eight pin connector on the PCB. The rear of the unit features three powerful rare-earth magnets that enable it to be attached to a vehicle.

Mark Csele’s complete portable accelerometer design, which he presented in Circuit Cellar 266. with the serial download adapter. The adapter is installed only when downloading data to a PC and mates with an eight pin connector on the PCB. The rear of the unit features three powerful
rare-earth magnets that enable it to be attached to a vehicle.

Trusting simulation (or, if you prefer, lack of testing under real conditions). I wrote the firmware for a large three-phase synchronous control system. The code performed amazingly well in the lab, and no matter what stimulus was applied, it always produced correct results. When put into operation in the field (at a very large industrial installation), it failed every 20 minutes or so, producing a massive (and dangerous) step-voltage output! I received a call from a panicked engineer on-site, and after an hour of diagnosis, I asked for a screenshot of the actual power line (which was said to be “noisy,” but we knew this ahead of time) only to be shocked at how noisy. Massive glitches appeared on the line many times larger than the AC peak and crossing zero several times, causing no end of problems. Many hours later (the middle of the morning), the software was fixed with a new algorithm that compensated for such “issues.” This was an incredibly humbling experience: I wasn’t nearly as smart as I had thought, and I really missed the boat on testing. I tested the system under what I thought were realistic conditions, whereas I really should have spent time investigating what the target grid really looked like.—Mark Csele, CC25 (anniversary issue)

High Dynamic-Range Audio Processor

STMicroelectronics recently introduced a new digital audio processor with greater than 100-dB SNR and Dynamic Range. The device can process most digital input formats including 6.1/7.1 channel and 192-kHz, 24-bit DVD audio and DSD/SACD. When configured in a 5.1 application, its additional two channels can be used to supply audio line-out or headphone drive.

Source: STMicroelectronics

Source: STMicroelectronics

The STA311B is a single chip solution for digital audio processing and control in multichannel applications, providing FFXTM (Full Flexible Amplification) compatible outputs. Together with a FFXTM power amplifier it can provide high-quality, high-efficiency, all-digital amplification.

The chip accepts digitized audio input information in either I2S (left or right justified), LSB or MSB first, with word lengths of 16, 18, 20 and 24 bits. Its pop-noise removal feature does not discriminate against the music genre but instead prevents any audible transients or pops finding their way through to the power amp where they may damage the speakers. Device control is via an I2C interface. The STA311B embeds eight audio-processing channels with up to 10 independent user-selectable bi-quadratic filters per channel to allow easy implementation of tone and music genre equalization templates. It is capable of input and output mixing with multi-band dynamic range compression. The chip also has input sampling frequency auto-detection, input/output RMS metering and employs pulse-width modulated output channels.

The STA311B is supplied in an 8.0 × 8.0 × 0.9 mm VFQFPN package.

[via Elektor]

Fanless Small Form Factor PC System

HABEYThe BIS-3922 improves on HABEY’s BIS-6922 system by offering additional I/O for more applications and solutions. The system is well suited for automation, digital signage, network security, point of sale, transportation, and digital surveillance applications.
The BIS-3922 system includes six DB9 COM ports on the front panel, one of which supports RS-232/-422/-485. HABEY’s proprietary ICEFIN design ensures maximum heat dissipation and a true fanless system.

The BIS-3922 system is built with the Intel QM77 chipset and is compatible with the third-generation Ivy Bridge Core processors. The BIS-3922 system’s additional features include a HM77 chipset that supports third-generation Intel Core i3/i5/i7 processors; dual gigabit Ethernet ports; High-Definition Multimedia Interface (HDMI), video graphics array (VGA), and low-voltage differential signaling (LVDS) display interfaces; one mini-PCI Express (PCIe) and one mSATA expansion; and a 3.5” single-board computer (SBC) form factor.

Contact HABEY for pricing.

HABEY USA, Inc.
www.habeyusa.com

3400-F Ultracapacitor

Maxwell Technologies has announced the addition of a 2.85-V, 3400-F cell to its K2 family of ultracapacitors. It is the most powerful cell available in the industry-standard, 60-mm cylindrical form factor. Incorporating Maxwell’s DuraBlue Advanced Shock and Vibration technology, it is a rugged cell that’s suitable for high-energy storage in demanding environments (e.g., in public transit vehicles).maxwell

The electrostatic charge can be cycled over a million times without performance degradation. The cells can also provide extended power and energy for long periods of propulsion in automotive subsystems and give fast response in UPS/Backup Power and grid applications to ensure critical information is not lost during dips, sags, and outages in the main power source. In addition, they can relieve batteries of burst power functions, thereby reducing costs and maximizing space and energy efficiency.

The K2 family of cells work in tandem with batteries for applications that require both a constant power discharge for continual function and a pulse power for peak loads. In these applications, the ultracapacitor relieves batteries of peak power functions resulting in an extension of battery life and a reduction of overall battery size and cost. The cells are available with threaded terminals or with compact, weldable terminals.

[via Elektor]

Wearable Medical Computing and the Amulet Project

Health care is one of the most promising areas for employing wearable devices. Wearable mobile health sensors can track activities (e.g., count steps or caloric expenditure), monitor vital signs including heart rate and blood pressure, measure biometric data (e.g., glucose levels and weight), and provide alerts to medical emergencies including heart failures, falls, and shocks.

Applying wearable computing to support mobile health (mHealth) is promising but involves significant risks. For instance, there are security issues related to the reliability of the devices and sensors employed, the accuracy of the data collected, and the privacy of sensitive information.

The Amulet bracelet-style prototype for developers enables users to control its settings

The Amulet bracelet-style prototype for developers enables users to control its settings

Under the federally funded Amulet project, an interdisciplinary team of Dartmouth College and Clemson University researchers is investigating how wearable devices can effectively address medical problems while ensuring wearability, usability, privacy, and security for mHealth applications. The project aims to develop pieces of “computational jewelry” and a software framework for monitoring them. This computational jewelry set comprises wearable mobile health devices collectively named Amulet. An Amulet device could be worn as a discreet pendant or bracelet that would interact with other wearable health sensors that constitute the wearer’s wireless body-area network (WBAN). The Amulet device would serve as a “hub,” tracking health information from wearable health sensors and securely sending data to other health devices or medical professionals.

The project’s goals are multifold. Regarding the hardware, we’re focusing on designing small and unobtrusive form factors, efficient power sources, and sensing capabilities. With respect to the software, we’re concentrating on processing and interpreting the digital signs coming from the sensors, effectively communicating and synchronizing data with external devices, and managing encrypted data.

Amulet’s multiprocessor hardware architecture includes an application processor that performs computationally intensive tasks and a coprocessor that manages radio communications and internal sensors. Amulet’s current prototypes contain an accelerometer and a gyroscope to monitor the wearer’s motion and physical activities, a magnetometer, a temperature sensor, a light sensor, and a microphone. To save power, the application processor is powered off most of the time, while the coprocessor handles all real-time device interactions.

By employing event-driven software architecture, Amulet enables applications to survive routine processor shutdowns. Amulet is reactive, running only when an event of interest occurs. To handle such events, programmers can define their application as a finite-state machine and set appropriate functions. Amulet’s architecture enables applications to identify the computational states that should be retained between events. Explicitly managing program state (rather than implicitly managing state in a thread’s run-time stack) enables the run-time system to efficiently save the application state to persistent memory and power down the main processor without harming applications.

Amulet provides a secure solution that ensures the accuracy and the integrity of the data sensed and transmitted, continuous availability of the services provided (e.g., data sensing and processing and sending alerts and notifications), and access to the device’s data and services only by authorized parties after their successful authentication. Two key features enable Amulet to provide security in mHealth applications: sandboxing and the authorization manager. The former enforces access control, protects memory, and restricts the execution of event handlers. The latter enables applications to run small tasks until their completion, managing all resources by receiving requests and forwarding them to a corresponding service manager.

Amulet also aims to protect privacy, enabling users to control what is sensed and stored, where it is stored, and how it is shared (with whom). Amulet devices use privacy policies to protect patients’ sensitive information, which ensures confidentiality through authorized access and controlled sharing.

To guarantee easy wearability, the Amulet team focuses on understanding the user’s wishes, needs, and requirements and translating them into appropriate design decisions. Amulet provides a list of principles and guidelines for wearability, which will aid designers in providing high levels of comfort, aesthetics, ergonomics, and discretion in their projects.

Amulet includes a framework to support stakeholders involved in similar projects during all phases of development. It is intended to aid developers and designers from industry or academia. Amulet provides a general-purpose solution for body-area mobile health, complementing the capabilities of a smartphone and facilitating the development of applications that integrate one or more mHealth wearable devices.

Amulet also provides intuitive interfaces and interaction methods for user input and output, employing multimodal approaches that include gestures and haptics. Amulet has developed and continues to refine bracelet-style prototypes with a variety of envisioned applications, including: emergency responders (e.g., providing immediate notifications and quick responses in medical emergencies), stress monitoring, smoking cessation, diet (e.g., bite counting), and physical therapy (e.g., knee sensors).

Dr. Vivian Genaro Motti

Dr. Vivian Genaro Motti

ABOUT THE AUTHOR

Dr. Vivian Genaro Motti holds a PhD in Human Computer Interaction from the Université catholique de Louvain in Belgium. She is a Postdoctoral Research Fellow in the School of Computing at Clemson University in Clemson, SC. She works on the Amulet project, which is funded by a three-year, $1.5 million grant from the National Science Foundation’s Computer Systems Research program. As part of the Amulet project, Vivian is investigating how to properly ensure wearability and privacy in wearable applications for mobile health. Vivian has a BA in Biomedical Informatics and an MS in Human Computer Interaction from University of Sao Paulo in Brazil. Her main research interests are human computer interaction, medical applications, wearable devices and context awareness.

This appears in Circuit Cellar 288, July 2014.

Microchip PICs with Integrated Crypto Engine

Anticipating the need for secure communications for the next level of device connectivity, Microchip Technology has integrated a complete hardware crypto engine into its PIC24F family of microcontrollers. Computers normally use software routines to carry out data encryption number crunching, but for low-power microcontrollers, this method will generally use up too much of the processor’s resources and be too slow.microchipPIC24FGB2

Microchip has integrated several security features into the PIC24F family of microcontrollers (identified by its “GB2″ suffix) to protect embedded data. The fully featured hardware crypto engine supports the AES, DES and 3DES standards to reduce software overhead, lower-power consumption, and enable faster throughput. A Random Number Generator is also implemented that can be used to create random keys for data encryption, decryption, and authentication to provide a high level of security. For additional protection, the one-time-programmable (OTP) key storage prevents the encryption key from being read or overwritten.

These security features increase the integrity of embedded data without sacrificing power consumption. With XLP technology, the “GB2” family achieves 180-µA/MHz run currents and 18-nA sleep currents for long battery life in portable applications.

[via Elektor]

Artisan’s Asylum

Artisan’s Asylum in Somerville, MA has the mission to promote and support the teaching, learning, and practicing of all varieties. Soumen Nandy is the Front Desk, General Volunteer, and Village Idiot of Artisan’s Asylum and she decided to tell us a little bit more about it.

1554402_785223821501448_2405207992407776899_n-artisansasylum

Photo courtesy of Artisan’s Asylum Facebook page

Location 10 Tyler St
Somerville, MA 02143
Members 400 active members
Website artisansasylum.com

Tell us about your meeting space!

We have around 40,000 sq. ft. that includes more than 150 studio spaces ranging from 50 sq. ft. to 200+ sq. ft. Our storage includes: lockers, 2 x 2 x 2 rack space, 40″ x 44″ pallets (up to 10′ tall), flexspace and studios. We have a truck-loading dock and a rail stop — yup, entire trains can pull up to our back doors for delivery. Can any other Maker Space say that? We also host a large roster of formal training courses in practical technologies, trades, crafts and arts, to help our members and the general community learn skills, and increase their awesomeness. (And not incidentally: become certified to safely use our gear.)

What are you working with?

Fully equipped wood, metal, machine, robotics, electronics, jewelry/glass shops, 12 sewing stations,  computer lab with all major professional modeling, CNC, and simulation packages (via direct partnerships with the respective companies). Multiple types of 3D printers, laser cutters, CNC routers, lathes, mills, etc. Too much more to list; if the Asylum doesn’t own/lease it, often a member, their business, or an institutional member can get it from you or get you access. And yet, it’s never enough.

Are there any tools your group really wants or needs?

Quite a few things, but it’s a delicate balance between sustainable operations, growth and space for member studios vs. facilities. We’ve spun off or attracted many companies, so the empty factory complex we moved into (until recently the worlds largest envelope factory) has almost completely filled up.

Does your group work with embedded tech (Arduino, Raspberry Pi, embedded security, MCU-based designs, etc.)?

Many of our members do. The group itself is too diverse to easily characterize.

What has your group been up to?

10464004_508974359203723_530424612314997460_n-artisanasylum-hexapod2

Hanging with a giant robot. (Courtesy of https://www.facebook.com/ProjectHexapod)

We’re not purely a technological space. We have artists, artisans, tradespesons, crafters, hobbyists, and technologists. I know of at least two-million dollar Kickstarters that launched from here. Hmmm… How about the 18-foot wide rideable-hexapod robot that’s nearing conclusion (we call it “Stompy“) or the 4′ x 8′ large format laser cutter that should be operational any day now? These are just some notably big projects, not necessarily our most awesome.

Oh, wait. we did an Ides of March Festival, dressing up Union Square as a Roman Forum.

What’s the craziest project your group or group members have completed?

Well, a few weeks ago, I went home at 10 PM, and woke to a tweeted photo announcing that this had been built in our social area; It’s actually not among our most surprising events, but it has reappeared several times since (fast dis/assembly), and a reporter caught it once. I just happened to receive this link a couple of hours ago, so it was handy to forward to you. We do a lot of art and participation projects around Boston.

What does Artisan’s social calendar look like these days?

Too many events to list! We’re really looking to stabilize our base, seek congruent funding donors (we are a non-profit, but thus far have mostly run on internally-earned income). I’d be happy to arrange an interview with one of our honchos if you like—the goings-ons around here are really too much to fit in one brain. Those of us who give tours actually regularly take each other’s tours to learn stuff about the place we never knew.

What would you like to say to fellow hackers out there?

Keep getting awesomer. We love you!

Also, any philanthropists out there? Our members and facilities could be an excellent way to multiply your awesome impact.

Keep up with Artisan’s Asylum! Check out their website!

Show us your hackerspace! Tell us about your group! Where does your group design, hack, create, program, debug, and innovate? Do you work in a 20′ × 20′ space in an old warehouse? Do you share a small space in a university lab? Do you meet at a local coffee shop or bar? What sort of electronics projects do you work on? Submit your hackerspace and we might feature you on our website!

Dutch Designer’s “Comfort Zone”

Check out this amusing workspace submission from Henk Stegeman who lives and works in The Netherlands (which is widely referred to as the land of Elektor). We especially like his Dutch-orange power strips, which stand out in relation to the muted grey, white, and black colors of his IT equipment and furniture. StegemanWorkspace

Some might call the space busy. Others might say it’s cramped. Stegeman referred to it his “comfort zone.” He must move and shift a lot of objects before he starts to design. But, hey, whatever works, right?

Hi,

Attached you picture of my workspace.
Where ? (you might ask.)
I just move the keyboard aside.
To where ?
Euuh… (good question)

Regards

Henk
The Netherlands

Visit Circuit Cellar‘s Workspace page for more write-ups and photos of engineering workbenches and tools from around the world!

Want to share your space? Email our editorial team pics and info about your spaces!

Specs & Code Matter (EE Tip #136)

No matter how many engineering hours you’ve logged over the years, it’s always a good idea to keep in mind that properly focusing on specs and code can make or break a project. In 2013, Aubrey Kagan—an experienced engineer and long-time Circuit Cellar author—explained this quite well in CC25:

There was a set of BCD thumbwheel switches that I was reading into a micro. In order to reduce the number of input lines required, each 4 bits of a digit was multiplexed with the other digits and selection was made by a transistor enabling the common line of each switch in turn. This was standard industry practice. The problem was that in order to economize, I had used the spare transistors in a Darlington driver IC. Everything worked fine in the lab, but on very hot days the unit would fail in the field with very strange results.

Long story short, the saturation voltage on the Darlington transistor would increase with temperature to above the digital input threshold and the micro would read undefined switch settings and then jump to non-existing code. I learned three things: read and understand all the specifications on a datasheet, things get a lot hotter in a cabinet in the sun than the lab, and you should make sure your code can handle conditions that are not supposed to occur.—Aubrey Kagan, CC25 (2o13)

Want to share an EE tip of your own? Email our editors to share your tips and tricks.

Fast Quad IF DAC

ADI AD9144 16-bit 2.8 GSPS DAC - Fastest Quad IF DAC - High DynaThe AD9144 is a four-channel, 16-bit, 2.8-GSPS DAC that supports high data rates and ultra-wide signal bandwidth to enable wideband and multiband wireless applications. The DAC features 82-dBc spurious-free dynamic range (SFDR) and a 2.8-GSPS maximum sample rate, which permits multicarrier generation up to the Nyquist frequency.

With –164-dBm/Hz noise spectral density, the AD9144 enables higher dynamic range transmitters to be built. Its low SFDR and distortion design techniques provide high-quality synthesis of wideband signals from baseband to high intermediate frequencies. The DAC features a JESD204B eight-lane interface and low inherent latency of fewer than two DAC clock cycles. This simplifies hardware and software system design while permitting multichip synchronization.

The combination of programmable interpolation rate, high sample rates, and low power at 1.5 W provides flexibility when choosing DAC output frequencies. This is especially helpful in meeting four- to six-carrier Global System for Mobile Communications (GSM) transmission specifications and other communications standards. For six-carrier GSM intermodulation distortion (IMD), the AD9144 operates at 77 dBc at 75-MHz IF. Operating with the on-chip phase-locked loop (PLL) at a 30-MHz DAC output frequency, the AD9144 delivers a 76-dB adjacent-channel leakage ratio (ACLR) for four-carrier Wideband Code Division Multiple Access (WCDMA) applications.

The AD9144 includes integrated interpolation filters with selectable interpolation factors. The dual DAC data interface supports word and byte load, enabling users to reduce input pins on lower data rates to save board space, power, and cost.

The DAC is supported by an evaluation board with an FPGA Mezzanine Card (FMC) connector, software, tools, a SPI controller, and reference designs. Analog Devices’s VisualAnalog software package combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface that enables users to customize their input signal and data analysis.

The AD9144BCPZ DAC costs $80. The AD9144-EBZ and AD9144-FMC-EBZ FMC evaluation boards cost $495.

Analog Devices, Inc.
www.analog.com

Robotics, Hardware Interfacing, and Vintage Electronics

Gerry O’Brien, a Toronto-based robotics and electronics technician at R.O.V. Robotics, enjoys working on a variety of projects in his home lab. His projects are largely driven by his passion for electronics hardware interfacing.

Gerry’s background includes working at companies such as Allen-Vanguard Corp., which builds remotely operated vehicle (ROV) robots and unmanned ground vehicles (UGVs) for military and police bomb disposal units worldwide. “I was responsible for the production, repair, programming and calibration of the robot control consoles, VCU (vehicle control unit) and the wireless communication systems,” he says.

Gerry recently sent Circuit Cellar photos of his home-based electronics and robotics lab. (More images are available on his website.) This is how he describes the lab’s layout and equipment:

In my lab I have various designated areas with lab benches that I acquired from the closing of a local Nortel  R&D office over 10 years ago.

All of my electronics benches have ESD mats and ground wrist straps.  All of my testing gear, I have purchased on eBay over the years….

PCB flip rack

PCB flip-rack

To start, I have my “Electronics Interfacing Bench” with a PCB flip-rack , which allows me to Interface PCBs while they are powered (in-system testing). I am able to interface my Tektronix TLA715 logic analyzer and other various testing equipment to the boards under test. My logic analyzer currently has two  logic I/O modules that have 136 channels each. So combined, I have 272 channels for logic analysis. I also have a four-channel digital oscilloscope module to use with this machine. I can now expand this even further by interfacing my newly acquired expansion box, which allows me to interface many more modules to the logic analyzer mainframe.

Gerry's lab bench

Gerry’s lab bench

Gerry recently upgraded his  Tektronix logic analyzer with an expansion box.

Gerry recently upgraded his Tektronix logic analyzer with an expansion box.

Interface probes

Logic analyzer interface probes

I also have a soldering bench where I have all of my soldering gear, including a hot-air rework station and 90x dissecting microscope with a video interface.

Dissecting microscope with video interface

Dissecting microscope with video interface

My devoted robotics bench has several robotic arm units, Scorbot and CRS robots with their devoted controllers and pneumatic Interface control boards.

Robotics bench

Robotics bench and CRS robot

On my testing bench, I currently have an Agilent/HP 54610B 500-MHz oscilloscope with the GPIB to RS-232 adapter for image capturing. I also have an Advantest model R3131A 9 kHz to 3-GHz bandwidth spectrum analyzer, a Tektronix model AFG3021 function generator, HP/Agilent 34401A multimeter and an HP 4CH programmable power supply. For the HP power supply, I built a display panel with four separate voltage output LCD displays, so that I can monitor the voltages of all four outputs simultaneously. The stock monochrome LCD display on the HP unit itself is very small and dim and only shows one output at a time.

Anyhow, my current testing bench setup will allow me to perform various signal mapping and testing on chips with a large pin count, such as the older Altera MAX9000 208-pin CPLDs and many others that I enjoy working with.

The testing bench

The testing bench

And last but not least… I have my programming and interfacing bench devoted to VHDL programming, PCB Design, FPGA hardware programming (JTAG), memory programming (EEPROM  and flash memory), web design, and video editing.

Interfacing bench and "octo-display"

Interfacing bench and “octo-display”

I built a PC computer and by using  a separate graphics display cards, one being an older Matrols four-port SVGA display card; I was able to build a “octo-display” setup. It seamlessly shares eight monitors providing a total screen resolution size of 6,545 x 1,980 pixels.

If you care to see how my monitor mounting assembly was built, I have posted pictures of its construction here.

A passion for electronics interfacing drives Gerry’s work:

I love projects that involve hardware Interfacing.  My area of focus is on electronics hardware compared to software programming. Which is one of the reasons I have focused on VHDL programming (hardware description language) for FPGAs and CPLDs.

I leave the computer software programming of GUIs to others. I will usually team up with other hobbyists that have more of a Knack for the Software programming side of things.  They usually prefer to leave the electronics design and hardware production to someone else anyhow, so it is a mutual arrangement.

I love to design and build projects involving vintage Altera CPLDs and FPGAs such as the Altera MAX7000 and MAX9000 series of Altera components. Over the years, I have a managed to collect a large arsenal of vintage Altera programming hardware from the late ’80s and early ’90s.  Mainly for the Altera master programming unit (MPU) released by Altera in the early ’90s. I have been building up an arsenal of the programming adapters for this system. Certain models are very hard to find. Due to the rarity of this Altera programming system, I am currently working on designing my own custom adapter interface that will essentially allow me to connect any compatible Altera component to the system… without the need of the unique adapter. A custom made adapter essentially.  Not too complicated at all really, it’s just a lot of fun to build and then have the glory of trying out other components.

I love to design, build, and program FPGA projects using the VHDL hardware description language and also interface to external memory and sensors. I have a devoted website and YouTube channel where I post various hardware repair videos or instructional videos for many of my electronics projects. Each project has a devoted webpage where I post the instructional videos along with written procedures and other information relating to the project. Videos from “Robotic Arm Repair” to a “DIY SEGA Game Gear Flash Cartridge” project. I even have VHDL software tutorials.

The last project I shared on my website was a project to help students dive into a VHDL based VGA Pong game using the Altera DE1 development board.

 

Switch Blade for Bandwidth-Demanding Applications

ADLINK_webThe aTCA-3710 is a 40G AdvancedTCA (ATCA) switch blade featuring a Broadcom BCM56846 10/40  gigabit Ethernet (GbE) fabric interface switch, a Broadcom BCM56334 24-port GbE base interface switch, and a Freescale QorIQ P2041 quad-core local management processor. The switch blade provides 14 10-GbE SFP+ uplink ports and supports 640-GBPS bandwidth for use in 14-slot 40G ATCA shelves. The aTCA-3710 is ideal for service providers requiring fast, high-quantity data throughput processing.

The aTCA-3710 40-GbE ATCA fabric interface switch blade is compliant with PICMG 3.0 R3.0 and PICMG 3.1 R2.0 standards. The high-performance server switch—along with CPU/NPU blades and ADLINK Software for Networks (ADSN)—can be used to constitute a 40G ARIP for next-generation applications. With a rich front panel I/O and a hot-swappable design, the aTCA-3710 guarantees high availability, scalability, and straightforward maintenance.

Contact ADLINK for pricing.

ADLINK Technology, Inc.
www.adlinktech.com

TinkerMill, where they share knowledge, lots of knowledge!

TM-Bothsides-1024x763

TinkerMill is a Hacker/Makerspace from Longmont, CO. Where like-minded people get together and collaborate on anything art, technology, science, and business related.

Scott Converse is the founder of TinkerMill and tells us about the organization.

Location 1250 S. Hover #49, Longmont, CO 80501
Members 65
Website tinkermill.org

What’s your meeting space like? 

Our workshop is over 6,500 square feet and we also have an office space.

What tools do you have in your space? 

  • Electronics
  • PCB board design
  • Robotics
  • Soldering stations
  • Woodworking shop
  • Metalworking shop
  • Welding shop
  • Rapid Prototyping
  • Lab (CNC, Lastercutter, 3D Printers)
  • Brewery & Distillery
  • Jewelry
  • Datacenter
  • And many more…

IMG_20140110_191201-tinkermill

Are there any tools your group really wants or needs?

Any PCB and pick/play stuff. Also some electronics supplies would be nice.

Does your group work with embedded tech like Arduino, Raspberry Pi, embedded security, or MCU-based designs?

We work with Arduino and Raspberry Pi a lot. Embedded stuff comes along quite often. For example we also work with Nvidia’s Jetson TK1 board, oDroid boards, and Parallella boards.

What are some of the projects your group has been working on?

We just did the Denver Mini Maker Faire. We also built a Tesla coil and we have about a dozen of other projects, which you can all find on our website.

What’s the craziest project your group or group members have completed?

For our craziest project so far I must say it was the 15 foot human-powered Ferris wheel. This was a great project!

What would you like to say to fellow hackers out there?

Come on down and BUILD something with us!

Want to know more about TinkerMill? Make sure to check out their website!

Show us your hackerspace! Tell us about your group! Where does your group design, hack, create, program, debug, and innovate? Do you work in a 20′ × 20′ space in an old warehouse? Do you share a small space in a university lab? Do you meet at a local coffee shop or bar? What sort of electronics projects do you work on? Submit your hackerspace and we might feature you on our website!

One-Wire RS-232 Half Duplex (EE Tip #135)

Traditional RS-232 communication needs one transmit line (TXD or TX), one receive line (RXD or RX), and a Ground return line. The setup allows a full-duplex communication. However, many applications use only half-duplex transmissions, as protocols often rely on a transmit/acknowledge scheme. With a simple circuit like Figure 1, this is achieved using only two wires (including Ground). This circuit is designed to work with a “real” RS-232 interface (i.e., using positive voltage for logic 0s and negative voltage for logic 1s), but by reversing the diodes it also works on TTL-based serial interfaces often used in microcontroller designs (where 0 V = logic 0; 5 V = logic 1). The circuit needs no additional voltage supply, no external power, and no auxiliary voltages from other RS-232 pins (RTS/CTS or DTR/DSR).Grun1-Wire-RS232-HalfDup

Although not obvious at a first glance, the diodes and resistors form a logic AND gate equivalent to the one in Figure 2 with the output connected to both receiver inputs. The default (idle) output is logic 1 (negative voltage) so the gate’s output follows the level of the active transmitter. The idle transmitter also provides the negative auxiliary voltage –U in Figure 2. Because both receivers are connected to one line, this circuit generates a local echo of the transmitted characters into the sender’s receiver section. If this is not acceptable, a more complex circuit like the one shown in Figure 3 is needed (only one side shown). This circuit needs no additional voltage supply either. In this circuit the transmitter pulls its associated receiver to logic 1 (i.e., negative voltage) by a transistor (any standard NPN type) when actively sending a logic 0 (i.e., positive voltage) but keeps the receiver “open” for the other transmitter when idle (logic 1). Here a negative auxiliary voltage is necessary which is generated by D2 and C1. Due to the start bit of serial transmissions, the transmission line is at logic 1 for at least one bit period per character. The output impedance of most common RS-232 drivers is sufficient to keep the voltage at C1 at the necessary level.

Note: Some RS-232 converters have quite low input impedance; the values shown for the resistors should work in the majority of cases, but adjustments may be necessary. In case of extremely low input impedance, the receiving input of the sender may show large voltage variations between 1s and 0s. As long as the voltage is below –3 V at any time these variations may be ignore.— Andreas Grün, “One Wire RS-232 Half Duplex,” Elektor July/August 2009.

Q&A: Teaching, CAD Research, and VLSI Innovation

Shiyan Hu is an assistant professor in the Department of Electrical and Computer Engineering at Michigan Technological University. We discussed his research in the fields of computer-aided design (CAD), very-large-scale integration (VSLI), smart home monitoring, and biochip design.—Nan Price, Associate Editor

 

Shiyan Hu

Shiyan Hu

NAN: How long have you been at Michigan Technological University? What courses do you currently teach and what do you enjoy most about instructing?

SHIYAN: I have been with Michigan Tech for six years as an assistant professor. Effective September 2014, I will be an associate professor.

I have recently taught the graduate-level “Advanced Embedded System for Smart Infrastructure,” the graduate-level “Advanced Very-Large-Scale Integration (VLSI) Computer-Aided Design (CAD),” and the undergraduate-level “VLSI Design” courses.
The most exciting part about teaching is the interactions with students. For example, questions from students—although sometimes challenging—can be intriguing and it is fun to observe diversified thoughts. In addition, students taking graduate-level courses need to discuss their course projects with me. During the discussions, I can clearly see how excited they feel about their progress, which makes the teaching very enjoyable.

NAN: What “hot topics” currently interest your students?

SHIYAN: Students are very interested in embedded system designs for smart homes, including FPGA design and embedded programming for the scheduling of various smart home appliances to improve convenience and reduce the cost of electricity bills. I also frequently have meetings with students who are interested in portable or wearable electronics targeting health-care applications.

Shiyan and a team of students he advises developed this sensor-based smart video monitoring system (left) and a 3-D mouse (right).

Photo 1: Shiyan and a team of students he advises developed this sensor-based smart video monitoring system.

Photo 2: A 3-D mouse developed by Shayin and his team.

Photo 2: A 3-D mouse developed by Shiyan and his team.

NAN: Describe your role as director of Michigan Tech’s VLSI CAD research lab.

SHIYAN: I have been advising a team of PhD and MS students who conduct research in the area of VLSI CAD in the Electrical and Computer Engineering (ECE) department. A main research focus of our lab is VLSI physical design including buffer insertion, layer assignment, routing, gate sizing, and so forth. In addition, we have developed some embedded system prototypes such as sensor-based video monitoring and a 3-D mouse (see Photos 1 and 2).

There is also growing collaboration between our lab and the power system lab on the research of a CAD technique for smart-grid systems. The collaboration has led to an innovative optimization technique for an automatic feeder remote terminal unit that addresses cybersecurity attacks to smart power distribution networks. Further, there is an ongoing joint project on an FPGA-based embedded system for power quality prediction.

Although most of my time as the research lab director is spent on student mentoring and project management, our lab also contributes considerably to education in our department. For example, instructional and lab materials for the undergraduate “VLSI Design” course are produced by our lab.

NAN: Tell us more about your smart home research and the technique you developed to address cybersecurity problems.

SHIYAN: My smart home research emphasizes embedded systems that handle scheduling and cybersecurity issues. Figure 1 shows a typical smart home system, which consists of various components such as household appliances, energy storage, photovoltaic (PV) arrays, and a plug-in hybrid electrical vehicle (PHEV) charger. Smart meters are installed at the customer side and connected to the smart power distribution system.

The smart meter can periodically receive updated pricing information from utility companies. The smart meter also has a scheduling unit that automatically determines the operation of each household appliance (e.g., the starting time and working power level), targeting the minimization of the monetary expense of each residential customer. This technology is called “smart home scheduling.”

In the real-time pricing model, utility pricing is determined by the load while the load is influenced by the pricing, forming a feedback loop. In this process, the pricing information is transmitted from the utility to the smart meters through some communication network, which could be wireless or wired. Cyber attackers can hack some access points in the transmission or just directly hack the smart meters. Those impacted smart meters would receive fake pricing information and generate the undesired scheduling solutions. Cyber attackers can take advantage of this by scheduling their own energy-consuming tasks during the inexpensive hours, which would be expensive without a cyber attack. This is an interesting topic I am working on.

This smart home system architecture includes HVAC and several home appliances.

Figure 1: This smart home system architecture includes HVAC and several home appliances.

NAN: Describe your VSLI research.

SHIYAN: Modern ICs and chips are ubiquitous. Their applications include smartphones, modern home appliances, PCs, and laptops, as well as the powerful servers for big data storage and processing. In VLSI and system-on-a-chip (SoC) design, the layout design (a.k.a., physical design) often involves billions of transistors and is therefore enormously complex. Handling such a complex problem requires high-performance software automation tools (i.e., physical design automation tools) to achieve design objectives within a reasonable time frame. VLSI physical design is a key part of my research area.

NAN: Are you involved in any other areas of research?

SHIYAN: I also work on microfluidic biochip design. The traditional clinical diagnosis procedure includes collecting blood from patients and then sending it to laboratories, which require space and are labor-intensive and expensive, yet sometimes inaccurate.

The invention of the lab on a chip (a.k.a., biochip) technology offers some relief. The expensive laboratory procedures can be simply performed within a small chip, which provides much higher sensitivity and detection accuracy in blood sample analysis and disease diagnosis. Some point-of-care versions of these have already become popular in the market.

A major weakness of the prevailing biochip technology is that such a chip often has very limited functionality in terms of the quantities it can measure. The reason is that currently only up to thousands of biochemical reactions can be handled in a single biochip. Since the prevailing biochips are always manually designed, this seems to be the best one can achieve. If a single biochip could simultaneously execute a few biological assays corresponding to related diseases, then the clinical diagnosis would be much less expensive and more convenient to conduct. This is also the case when utilizing biochips for biochemical research and drug discovery.

My aim for this biochip research project is to largely improve the integration complexity of miniaturized components in a biochip to provide many more functionalities. The growing design complexity has mandated a shift from the manual design process toward a CAD process.

Basically, in the microfluidic biochip CAD methodology, those miniaturized components, which correspond to fundamental biochemical operations (e.g., mix and split), are automatically placed and routed using computer algorithms. This methodology targets minimizing the overall completion time of all biochemical operations, limiting the sizes of biochips, and improving the yield in the biochip fabrication. In fact, some results from our work were recently featured on the front cover of IEEE Transactions on Nanobioscience (Volume 13, No. 1, 2014), a premier nanobioscience and engineering journal. In the future, we will consider inserting on-chip optical sensors to provide real-time monitoring of the biological assay execution, finding possible errors during execution, and dynamically reconfiguring the biochip for error recovery.

NAN: You’ve earned several distinctions and awards over the last few years. How do these acknowledgments help your research?

SHIYAN: Those awards and funding certainly help me a lot in pursuing the research of fascinating topics. For example, I am a 2014 recipient of the NSF CAREER award, which is widely regarded as one of the most prestigious honors for up-and-coming researchers in science and engineering.

My five-year NSF CAREER project will focus on carbon nanotube interconnect-based circuit design. In the prevailing 22-nm technology node, wires are made from coppers and such a thin copper wire has a very small cross-section area. This results in large wire resistance and large interconnect delay. In fact, the interconnect delay has become the limiting factor for chip timing. Due to the fundamental physical limits of copper wires, novel on-chip interconnect materials (e.g., carbon nanotubes and graphene nanoribbons) are more desirable due to their many salient features (e.g., superior conductivity and resilience to electromigration).

To judiciously integrate the benefits from both nanotechnology interconnects and copper interconnects, my NSF CAREER project will develop a groundbreaking physical layout codesign methodology for next-generation ICs. It will also develop various physical design automation techniques as well as a variation-aware codesign technique for the new methodology. This project aims to integrate the pioneering nanotechnologies into the practical circuit design and it has the potential to contribute to revolutionizing the prevailing circuit design paradigm.

NAN: Give us some background information. When did you first become interested in computer engineering?

SHIYAN: I started to work on computer engineering when I entered Texas A&M University conducting research with professor Jiang Hu, a leading expert in the field of VLSI physical design. I learned a lot about VLSI CAD from him and I did several interesting research projects including buffer insertion, gate sizing, design for manufacturability, and post silicon tuning. Through his introduction, I also got the chance to collaborate with leading experts from IBM Research on an important project called “slew buffering.”

NAN: Tell us more about your work at IBM Research.

SHIYAN: As VLSI technology scales beyond the 32-nm node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem.
Buffer insertion, which improves an IC’s timing performance by inserting non-inverting buffers or inverting buffers (a.k.a., inverters), has proven to be indispensable in interconnect optimization. It has been well documented that typically more than 25% of gates are buffers in IBM ASIC designs.

Together with my collaborators at IBM Research, I proposed a new slew buffering-driven dynamic programming technique. The testing with IBM ASIC designs demonstrated that our technique achieves a more than 100× speed increase compared to the classical buffering technique while still saving buffers. Therefore, the slew buffering-driven technique has been implemented and deployed into the IBM physical design flow as a default option.

IBM researchers have witnessed that the slew buffering technique contributes to a great reduction in the turnaround time of the physical synthesis flow. In addition, more extensive deployment of buffering techniques leads to superior design quality. Such an extensive buffer deployment-based interconnect synthesis was not possible prior to this work, due to the inefficiency of the previous buffering techniques.

After the publication of this work, various extensions to the slew buffering-driven technique were developed by other experts in the field. In summer 2010, I was invited by the group again to take a visiting professorship working on physical design, which resulted in a US patent being granted.