A Wire Is an Inductor (EE Tip #126)

I’m confident you know that you should keep wires and PCB tracks as short as possible. But I’m also sure that you will underestimate this problem fairly frequently.

Remember that 1 cm of a 0.25-mm-wide PCB track is roughly equivalent to an inductance of 10 nH. If this 10 nH is paired with, say, a 10-pF capacitor, that gives a resonant frequency as low as 500 MHz, which is easily below the third or fifth harmonics of the clock frequencies commonly seen on modern high-speed digital boards. Similarly, a 1-cm-long track will jeopardize the performances of any RF system such as a 2.4-GHz transceiver. There is only one solution: keep tracks and wires as short as possible. If you can’t, then use impedance-matched tracks.

Remember this rule especially for the ground connections: any grounded pad of any part working in high frequencies should be directly connected by avia to the underlying ground plane. And this via must be as close as possible to the pad, not some millimeters away.

Just yesterday I did a design review of a customer’s RF PCB. A small 0402 inductance was grounded through a via that was 3 mm away. It was a bad idea because the inductance was as low as 1 nH. Those 3 mm changed its value completely.—Robert Lacoste, “Mixed-Signal Designs,” CC25:25th Anniversary Issue, 2013. 

Client Profile: Integrated Knowledge Systems

Integrated Knowledge Systems' NavRanger board

Integrated Knowledge Systems’ NavRanger board

Phoenix, AZ

CONTACT: James Donald, james@iknowsystems.com
www.iknowsystems.com

EMBEDDED PRODUCTS: Integrated Knowledge Systems provides hardware and software solutions for autonomous systems.
featured Product: The NavRanger-OEM is a single-board high-speed laser ranging system with a nine-axis inertial measurement unit for robotic and scanning applications. The system provides 20,000 distance samples per second with a 1-cm resolution and a range of more than 30 m in sunlight when using optics. The NavRanger also includes sufficient serial, analog, and digital I/O for stand-alone robotic or scanning applications.

The NavRanger uses USB, CAN, RS-232, analog, or wireless interfaces for operation with a host computer. Integrated Knowledge Systems can work with you to provide software, optics, and scanning mechanisms to fit your application. Example software and reference designs are available on the company’s website.

EXCLUSIVE OFFER: Enter the code CIRCUIT2014 in the “Special Instructions to Seller” box at checkout and Integrated Knowledge Systems will take $20 off your first order.


 

Circuit Cellar prides itself on presenting readers with information about innovative companies, organizations, products, and services relating to embedded technologies. This space is where Circuit Cellar enables clients to present readers useful information, special deals, and more.

A Workspace for “Engineering Magic”

Brandsma_workspace2

Photo 1—Brandsma describes his workspace as his “little corner where the engineering magic happens.”

Sjoerd Brandsma, an R&D manager at CycloMedia, enjoys designing with cameras, GPS receivers, and transceivers. His creates his projects in a small workspace in Kerkwijk, The Netherlands (see Photo 1). He also designs in his garage, where he uses a mill and a lathe for some small and medium metal work (see Photo 2).

Brandsma_lathe_mill

Photo 2—Brandsma uses this Weiler lathe for metal work.

The Weiler lathe has served me and the previous owners for many years, but is still healthy and precise. The black and red mill does an acceptable job and is still on my list to be converted to a computer numerical control (CNC) machine.

Brandsma described some of his projects.

Brandsma_cool_projects

Photo 3—Some of Brandsma’s projects include an mbed-based camera project (left), a camera with an 8-bit parallel databus interface (center), and an MP3 player that uses a decoder chip that is connected to an mbed module (right).

I built a COMedia C328 UART camera with a 100° lens placed on a 360° servomotor (see Photo 3, left).  Both are connected to an mbed module. When the system starts, the camera takes a full-circle picture every 90°. The four images are stored on an SD card and can be stitched into a panoramic image. I built this project for the NXP mbed design challenge 2010 but never finished the project because the initial idea involved doing some stitching on the mbed module itself. This seemed to be a bit too complicated due to memory limitations.

I built this project built around a 16-MB framebuffer for the Aptina MT9D131 camera (see Photo 3, center). This camera has an 8-bit parallel databus interface that operates on 6 to 80 MHz. This is way too fast for most microcontrollers (e.g., Arduino, Atmel AVR, Microchip Technology PIC, etc.). With this framebuffer, it’s possible to capture still images and store/process the image data at a later point.

This project involves an MP3 player that uses a VLSI VS1053 decoder chip that is connected to an mbed module (see Photo 3, right). The great thing about the mbed platform is that there’s plenty of library code available. This is also the case for the VS1053. With that, it’s a piece of cake to build your own MP3 player. The green button is a Skip button. But beware! If you press that button it will play a song you don’t like and you cannot skip that song.

He continued by describing his test equipment.

Brandma_test_equipment

Photo 4—Brandsma’s test equipment collection includes a Tektronix TDS220 oscilloscope (top), a Total Phase Beagle protocol analyzer (second from top), a Seeed Technology Open Workbench Logic Sniffer (second from bottom), and a Cypress Semiconductor CY7C68013A USB microcontroller (bottom).

Most of the time, I’ll use my good old Tektronix TDS220 oscilloscope. It still works fine for the basic stuff I’m doing (see Photo 4, top). The Total Phase Beagle I2C/SPI protocol analyzer Beagle/SPI is a great tool to monitor and analyze I2C/SPI traffic (see Photo 4, second from top).

The red PCB is a Seeed Technology 16-channel Open Workbench Logic Sniffer (see Photo 4, second from bottom). This is actually a really cool low-budget open-source USB logic analyzer that’s quite handy once in a while when I need to analyze some data bus issues.

The board on the bottom is a Cypress CY7C68013A USB microcontroller high-speed USB peripheral controller that can be used as an eight-channel logic analyzer or as any other high-speed data-capture device (see Photo 4, bottom). It’s still on my “to-do” list to connect it to the Aptina MT9D131 camera and do some video streaming.

Brandsma believes that “books tell a lot about a person.” Photo 5 shows some books he uses when designing and or programming his projects.

Brandsma_books

Photo 5—A few of Brandsma’s “go-to” books are shown.

The technical difficulty of the books differs a lot. Electronica echt niet moeilijk (Electronics Made Easy) is an entry-level book that helped me understand the basics of electronics. On the other hand, the books about operating systems and the C++ programming language are certainly of a different level.

An article about Brandsma’s Sun Chaser GPS Reference Station is scheduled to appear in Circuit Cellar’s June issue.

Compact Computer-on-Module

ADLINKThe cExpress-HL computer-on-module (COM) utilizes an Intel Core processor (formerly known as Haswell-ULT) to provide a compact, high-performance COM solution. The cExpress-HL is well suited for embedded systems in medical, digital signage, gaming, video conferencing, and industrial automation that require a high-performance CPU and graphics, but are constrained by size or thermal management requirements.

The cExpress-HL features a mobile 4th Generation Intel Core i7/i5/i3 processor at 1.7 to 3.3 GHz with Intel HD Graphics 5000 (GT3). The COM delivers high graphics performance while still keeping thermal design power (TDP) below 15 W. Intel’s system-on-chip (SoC) solution has a small footprint that enables it to fit onto the 95 mm × 95 mm COM.0 R2.0 Type 6. The COM provides rich I/O and wide-bandwidth data throughput, including three independent displays (two DDI channels and one LVDS), four PCIe x1 or one PCIe x4 (Gen2), four SATA 6 Gb/s, two USB 3.0 ports, and six USB 2.0 ports.

The cExpress-HL is equipped with ADLINK’s Smart Embedded Management Agent (SEMA), which includes a watchdog timer, temperature and other board information monitoring, and fail-safe BIOS support. SEMA enables users to monitor and manage stand-alone, connected, or remote systems through a cloud-based interface.
Contact ADLINK for pricing.

ADLINK Technology, Inc.
www.adlinktech.com

All-Programmable SoC Solution

Anyone creating a complex, powerful digital design may want to turn to a single device that integrates high-speed processing and programmable logic.

In Circuit Cellar’s April issue, columnist Colin O’Flynn explores using the Xilinx Zynq  Z-7020 All Programmable SoC (system-on-a-chip) as part of the Avnet ZedBoard development board.

“I used a Xilinx Zynq SoC device, although Altera offers several flavors of a similar device (e.g., the Cyclone V SoC, the Arria V SoC, and the Arria 10 SoC), and Microsemi offers the SmartFusion2 SoC FPGA,” O’Flynn says in his article. “The Xilinx and Altera devices feature a dual-core ARM Cortex-A9 processor, whereas the Microsemi devices feature a less powerful Cortex-M3 processor. You may not need a dual-core A9 processor, so ‘less powerful’ may be an advantage.”

While O’Flynn’s article introduces the ZedBoard, he notes many of its specifics also apply to the MicroZed board, a less expensive option with a smaller SoC. Xilinx’s Zynq device has many interesting applications made highly accessible through the ZedBoard and MicroZed boards, he says.

O’Flynn’s discussion of the Zynq SoC device includes the following excerpt. (The April issue, which includes O’Flynn’s full article, is available for membership download or single-issue purchase.)

WHERE’S THE BEEF?
Originally, I had planned to describe a complete demo project in this article. I was going to demonstrate how to use a combination of a custom peripheral and some of the hard cores to stream data from a parallel ADC device into DDR memory. But there wasn’t enough room to introduce the tools and cover the demo, so I decided to introduce the Zynq device (using the ZedBoard).

A demo project is available at ProgrammableLogicInPractice.com. Several tutorials for the Zynq device are available at xilinx.com and zedboard.org, so there isn’t any point in duplicating work! I’ve linked to some specific tutorials from the April 2014 post on ProgrammableLogicInPractice.com. Photo 1 shows the hardware I used, which includes a ZedBoard with my custom OpenADC board connected through the I/O lines.

An Avnet ZedBoard is connected to the OpenADC. The OpenADC provides a moderate-speed ADC (105 msps), which interfaces to the programmable logic (PL) fabric in Xilinx’s Zynq device via a parallel data bus. The PL fabric then maps itself as a peripheral on the hard-core processing system (PS) in the Zynq device to stream this data into the system DDR memory.

Photo 1: An Avnet ZedBoard is connected to the OpenADC. The OpenADC provides a moderate-speed ADC (105 msps), which interfaces to the programmable logic (PL) fabric in Xilinx’s Zynq device via a parallel data bus. The PL fabric then maps itself as a peripheral on the hard-core processing system (PS) in the Zynq device to stream this data into the system DDR memory.

FPGA PROCESSOR DESIGN 101
Even if you’re experienced in FPGA design, you may not have used Xilinx tools for processor-specific design. These tools include the Xilinx Platform Studio (XPS) and the Xilinx Software Development Kit (SDK). Before the advent of hard-core processors (e.g., Zynq), there have long existed soft-core processors, including the popular Xilinx MicroBlaze soft processor. The MicroBlaze system is completely soft core, so you can use the XPS tool to define the peripherals you wish to include. For the Zynq device, several hard-core peripherals are always present and you can choose to add additional soft-core (i.e., use the FPGA fabric) peripherals.

In a future article I will discuss different soft-core processor options, including some open-source third-party ones that can be programmed from the Arduino environment. For now, I’ll examine only the Xilinx tools, which are applicable to the Zynq device, along with the MicroBlaze core.

The ARM cores in the Zynq device are well suited to run Linux, which gives you a large range of existing code and tools to use in your overall solution. If you don’t need those tools, you can always run on “bare metal” (e.g., without Linux), as the tools will generate a complete base project for you that compiles and tests the peripherals (e.g., printing “Hello World” out the USART). To give you a taste of this, I’ve posted a demo video of bringing up a simple “Hello World” project in both Linux and bare metal systems on ProgrammableLogicInPractice.com.

The FPGA part of the Zynq device is called the programmable logic (PL) portion. The ARM side is called the processing system (PS) portion. You will find a reference to the SoC’s PL or PS portion throughout most of the tutorials (along with this article), so it’s important to remember which is which!

For either system, you’ll be starting with the XPS software (see Photo 2). This software is used to design your hardware platform (i.e., the PL fabric), but it also gives you some customization of the PS hard-core peripherals.

This is the main screen of the Xilinx Platform Studio (XPS) when configuring a Zynq design. On the left you can see the list of available soft-core peripherals to add to the design. You can configure any of the hard-core peripherals by choosing to enable or disable them, along with selecting from various possible I/O connections. Additional screens (not shown) enable you to configure peripherals addressing information, configure I/O connections for the soft-core peripherals, and connect peripherals to various available extension buses.

Photo 2: This is the main screen of the Xilinx Platform Studio (XPS) when configuring a Zynq design. On the left you can see the list of available soft-core peripherals to add to the design. You can configure any of the hard-core peripherals by choosing to enable or disable them, along with selecting from various possible I/O connections. Additional screens (not shown) enable you to configure peripherals addressing information, configure I/O connections for the soft-core peripherals, and connect peripherals to various available extension buses.

MAKING THE CONNECTION
For example, clicking on the list of hard-core peripherals opens the options dialogue so you can enable or disable each peripheral along with routing the I/O connections. The ZedBoard’s Zynq device has 54 multipurpose I/O (MIO) lines that can be used by the peripherals, which are split into two banks. Each bank can use different I/O standards (e.g., 3.3 and 1.5 V).

Enabling all the peripherals would take a lot more than 54 I/O lines. Therefore, most of the I/O lines share multiple functions on the assumption that every peripheral doesn’t need to be connected. Many of the peripherals can be connected to several different I/O locations, so you (hopefully) don’t run into two peripherals needing the same I/O pin.

Almost all of the peripheral outputs can be routed to the PL fabric as well under the name EMIO, which is a dedicated 64-bit bus that connects to the PL fabric. If you simply wish to get more I/O pins, you can configure these extra pins from within XPS. But you can also use this EMIO bus to control existing cores in your FPGA fabric using peripherals on the Zynq device.

Assume you had an existing FPGA design where you had an FPGA core doing some processing connected to a microcontroller or computer via I2C, SPI, or serial. You could simply connect this core to the appropriate PS peripheral and port the existing code onto the Zynq processor by changing the low-level calls to use the Zynq peripherals. You may eventually wish to change this interface to the peripheral bus, the AMBA Advanced eXtensible Interface (AXI), for better performance. However, using standard peripherals to interface to a PL design can still be useful for many cores for which you have extensive existing code.

The MIO/EMIO pins can even be used in a bit-banging fashion, so if you need a special device or core control logic, it’s possible to quickly develop this in software. You can then move to a hardware peripheral for considerably better performance.

O’Flynn’s article goes on to discuss in greater detail the internal buses, peripherals, and taking a design from hardware to software. For more, refer to Circuit Cellar‘s  April issue and related application notes posted at O’Flynn’s companion site ProgrammableLogicInPractice.com.