RS-232 Serial Adapter for Android Devices

ACCESSThe ANDROID-232 is a USB serial interface board that enables you to control legacy RS-232 devices from your Android devices. The board is well suited for POS, gaming systems, retail, hospitality, automation, kiosks, defense industries, lighting, or any other application requiring the connection of RS-232 serial devices to an Android-compatible system.

The ANDROID-232 uses the Android Open Accessory protocol to “convince” an Android device that its on-board USB port (normally limited to USB slave or OTG modes) is actually an RS-232 port. This two-way data port enables external hardware to control the Android unit or the Android unit to control external hardware.

The ANDROID-232’s key features include an Android USB 2.0 full-speed host-to-industry-standard RS-232 DB9M serial port; support for a UART interface with RX, TX, RTS, and CTS; a 5,512-byte RX buffer size; a 256-byte TX buffer size; ±15-kV ESD protection on USB data lines and all RS-232 signals; status and fault LEDs including external power, charging status, and USB status; a Type-A USB connector; a latching 5-V external power input connector with an external regulated power supply; a –40°C-to-85°C standard industrial operating temperature; and RoHS compliance.

The board includes an Android sample program with source code. This program enables you to verify proper operation of the ANDROID-232 device, including sending and receiving RS-232 data. The ANDROID-232’s Python test program can cooperate with the Android sample program to verify proper receipt of transmitted data.

The ANDROID-232 costs $139.

ACCES I/O Products, Inc.
www.accesio.com

3-D Integration Impact and Challenges

People want transistors—lots of them. It pretty much doesn’t matter what shape they’re in, how small they are, or how fast they operate. Simply said, the more the merrier. Diversity is also good. The more different the transistors, the more useful and interesting the product. And without any question, the cheaper the transistors, the better. So the issue is, how best to achieve as many diverse transistors at the lowest cost possible.

One approach is more chips. Placing a lot of chips close together on a small board will produce a system with many transistors. Another way is more transistors per chip. Keep on scaling the technology to provide more transistors in one or a few chips.

silicon chipThe third option combines these two approaches. Let’s have many chips with many transistors and end up with a huge number of transistors. However, there is a limit to this approach. It’s well understood that scaling is coming to an end. And placing multiple chips on a board can have a terrible effect on a system’s overall speed and power dissipation.

But there is an elegant and intellectually simple solution. Rather than connecting these chips horizontally across a board, connect them vertically, providing N times more transistors, where N is the number of chips stacked one above another. Such vertical, 3-D integration was first broached by William Shockley, co-inventor of the transistor at Bell Labs in 1947. Shockley described the 3-D integration concept in a 1958 patent, which was followed by Merlin Smith and Emanuel Stern’s 1967 patent outlining how best to produce the holes between layers. We now call these inter-layer holes through silicon vias (TSVs). Technology is still catching up to these 3-D concepts.

Three-dimensional integration offers exciting advantages. For example, the vertical distance between layers is much shorter than the horizontal dimensions across a chip. Three-dimensional circuits, therefore, operate faster and dissipate less power than their 2-D equivalent. A 3-D system is shockingly small, permitting it to fit much more conveniently into a tiny space. Think small portable electronics (e.g., credit cards).

But the most exciting advantage of 3-D integration isn’t the small form factor, higher speed, or lower power; it’s the natural ability to support many disparate technologies and functions as one integrated, heterogeneous system. Even better, each chip layer can be optimized for a particular function and technology, since the individual chips can each be developed in isolation. No more trading off different capabilities to combine disparate technologies on the same chip. Now we can use the absolute best technology for each layer and a completely different and optimized technology for a different layer. This approach enables all kinds of novel applications that until now couldn’t have been conceived or would have been cost-prohibitive.

Imagine placing a microprocessor plane below a MEMS-accelerometer plane below an analog plane (with ADCs) below a temperature sensor, all below a video imager (which has to be at the top to “see”). All of these planes fit together into a tiny (smaller than a fingernail) silicon cube while operating at higher speeds and dissipating lower power.

There are technical issues, including: how to best make the TSVs, how to construct the system architecture to fully exploit the system’s 3-D nature, how to deliver power across these multiple planes, how to synchronize this system to best move data around the cube, how to manage system design complexity, and much more.

Two issues rise to the top. The first is power dissipation (specifically, power density). When many transistors switch at a high rate within a tiny volume, the temperature rises, which can impair performance and reliability. I believe this issue, albeit difficult, is technically solvable and simply will require a lot of good engineering.

The real problem is cost. How do we mature this technology quickly enough to drive the costs down to a point where volume commercial applications are possible? Many companies are close to producing tangible 3-D-based products. Cubes of highly dense memory will likely be the first serious and cost-effective product. Early versions are already available. Three-dimensional integration will soon be here in a serious way with what will be a fascinating assortment of all kinds of exciting new products. You won’t have to wait too long.

Evaluating Oscilloscopes (Part 4)

In this final installment of my four-part mini-series about selecting an oscilloscope, I’ll look at triggering, waveform generators, and clock synchronization, and I’ll wrap up with a series summary.

My previous posts have included Part 1, which discusses probes and physical characteristics of stand-alone vs. PC-based oscilloscopes; Part 2, which examines core specifications such as bandwidth, sample rate, and ADC resolution; and Part 3, which focuses on software. My posts are more a “collection of notes” based on my own research rather than a completely thorough guide. But I hope they are useful and cover some points you might not have otherwise considered before choosing an oscilloscope.

This is a screenshot from Colin O'Flynn's YouTube video "Using PicoScope AWG for Testing Serial Data Limits."

This is a screenshot from Colin O’Flynn’s YouTube video “Using PicoScope AWG for Testing Serial Data Limits.”

Topic 1: Triggering Methods
Triggering your oscilloscope properly can make a huge difference in being able to capture useful waveforms. The most basic triggering method is just a “rising” or “falling” edge, which almost everyone is (or should be) familiar with.

Whether you need a more advanced trigger method will depend greatly on your usage scenario and a bit on other details of your oscilloscope. If you have a very long buffer length or ability to rapid-fire record a number of waveforms, you might be able to live with a simple trigger since you can easily throw away data that isn’t what you are looking for. If your oscilloscope has a more limited buffer length, you’ll need to trigger on the exact moment of interest.

Before I detail some of the other methods, I want to mention that you can sometimes use external instruments for triggering. For example, you might have a logic analyzer with an extremely advanced triggering mechanism.  If that logic analyzer has a “trigger out,” you can trigger the oscilloscope from your logic analyzer.

On to the trigger methods! There are a number of them related to finding “odd” pulses: for example, finding glitches shorter or wider than some length or finding a pulse that is lower than the regular height (called a “runt pulse”). By knowing your scope triggers and having a bit of creativity, you can perform some more advanced troubleshooting. For example, when troubleshooting an embedded microcontroller, you can have it toggle an I/O pin when a task runs. Using a trigger to detect a “pulse dropout,” you can trigger your oscilloscope when the system crashes—thus trying to see if the problem is a power supply glitch, for example.

If you are dealing with digital systems, be on the lookout for triggers that can function on serial protocols. For example, the Rigol Technologies stand-alone units have this ability, although you’ll also need an add-on to decode the protocols! In fact, most of the serious stand-alone oscilloscopes seem to have this ability (e.g., those from Agilent, Tektronix, and Teledyne LeCroy); you may just need to pay extra to enable it.

Topic 2: External Trigger Input
Most oscilloscopes also have an “external trigger input.”  This external input doesn’t display on the screen but can be used for triggering. Specifically, this means your trigger channel doesn’t count against your “ADC channels.” So if you need the full sample rate on one channel but want to trigger on another, you can use the “ext in” as the trigger.
Oscilloscopes that include this feature on the front panel make it slightly easier to use; otherwise, you’re reaching around behind the instrument to find the trigger input.

Topic 3: Arbitrary Waveform Generator
This isn’t strictly an oscilloscope-related function, but since enough oscilloscopes include some sort of function generator it’s worth mentioning. This may be a standard “signal generator,” which can generate waveforms such as sine, square, triangle, etc. A more advanced feature, called an arbitrary waveform generator (AWG), enables you to generate any waveform you want.

I previously had a (now very old) TiePie engineering HS801 that included an AWG function. The control software made it easy to generate sine, square, triangle, and a few other waveforms. But the only method of generating an arbitrary waveform was to load a file you created in another application, which meant I almost never used the “arbitrary” portion of the AWG. The lesson here is that if you are going to invest in an AWG, make sure the software is reasonable to use.

The AWG may have a few different specifications; look for the maximum analog bandwidth along with the sample rate. Be careful of outlandish claims: a 200 MS/s digital to analog converter (DAC) could hypothetically have a 100-MHz analog bandwidth, but the signal would be almost useless. You could only generate some sort of sine wave at that frequency, which would probably be full of harmonics. Even if you generated a lower-frequency sine wave (e.g., 10 MHz), it would likely contain a fair amount of harmonics since the DAC’s output filter has a roll-off at such a high frequency.

Better systems will have a low-pass analog filter to reduce harmonics, with the DAC’s sample rate being several times higher than the output filter roll-off. The Pico Technology PicoScope 6403D oscilloscope I’m using can generate a 20-MHz signal but has a 200 MS/s sample rate on the DAC. Similarly, the TiePie engineering HS5-530 has a 30-MHz signal bandwidth, and similarly uses a 240 MS/s sample rate. A sample rate of around five to 10 times the analog bandwidth seems about standard.

Having the AWG integrated into the oscilloscope opens up a few useful features. When implementing a serial protocol decoder, you may want to know what happens if the baud rate is slightly off from the expected rate. You can quickly perform this test by recording a serial data packet on the oscilloscope, copying it to the AWG, and adjusting the AWG sample rate to slightly raise or lower the baud rate. I illustrate this in the following video.


Topic 4: Clock Synchronization

One final issue of interest: In certain applications, you may need to synchronize the sample rate to an external device. Oscilloscopes will often have two features for doing this. One will output a clock from the oscilloscope, the other will allow you to feed an external clock into the oscilloscope.

The obvious application is synchronizing a capture between multiple oscilloscopes. You can, however, use this for any application where you wish to use a synchronous capture methodology. For example, if you wish to use the oscilloscope as part of a software-defined radio (SDR), you may want to ensure the sampling happens synchronous to a recovered clock.

The input frequency of this clock is typically 10 MHz, although some devices enable you to select between several allowed frequencies. If the source of this clock is anything besides another instrument, you may have to do some clock conditioning to convert it into one of the valid clock source ranges.

Summary and Closing Comments
That’s it! Over the past four weeks I’ve tried to raise a number of issues to consider when selecting an oscilloscope. As previously mentioned, the examples were often PicoScope-heavy simply because it is the oscilloscope I own. But all the topics have been relevant to any other oscilloscope you may have.

You can check out my YouTube playlist dealing with oscilloscope selection and review.  Some topics might suggest further questions to ask.

I’ve probably overlooked a few issues, but I can’t cover every possible oscilloscope and option. When selecting a device, my final piece of advice is to download the user manual and study it carefully, especially for features you find most important. Although the datasheet may gloss over some details, the user manual will typically address the limitations you’ll run into, such as FFT length or the memory depths you can configure.

Author’s note: Every reasonable effort has been made to ensure example specifications are accurate. There may, however, be errors or omissions in this article. Please confirm all referenced specifications with the device vendor.

Client Profile: ImageCraft Creations, Inc.

CorStarter prototyping board

CorStarter prototyping board

2625 Middlefield Road, #685,
Palo Alto, CA 94306

CONTACT: Richard Man,
richard@imagecraft.com
imagecraft.com

EMBEDDED PRODUCTS:ImageCraft Version 8 C compilers with an IDE for Atmel AVR and Cortex M devices are full-featured toolsets backed by strong support.

CorStarter-STM32 is a complete C hardware and software kit for STM32 Cortex-M3 devices. The $99 kit includes a JTAG pod for programming and debugging.

ImageCraft products offer excellent features and support within budget requisitions. ImageCraft compiler toolsets are used by professionals who demand excellent code quality, full features, and diligent support in a timely manner.

The small, fast compilers provide helpful informational messages and include an IDE with an application builder (Atmel AVR) and debugger (Cortex-M), whole-program code compression technology, and MISRA safety checks. ImageCraft offers two editions that cost $249 and $499.

The demo is fully functional for 45 days, so it is easy to test it yourself.

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DDS Basics (EE Tip #122)

The simplest form of a digital waveform synthesizer is a table look-up generator (see Figure 1). Just program a period of the desired waveform in a digital memory (Why not an EPROM for old timers?), connect a binary counter to the address lines of the memory, connect a DAC to the memory data lines, keep the memory in Read mode, clock the counter with a fixed-frequency oscillator FCLOCK, and voilà, you’ve got a waveform on the DAC output. Don’t forget to add a low-pass filter to clean the output signal, with, as you know, a cut-off frequency a little less than FCLOCK/2 to please Mr. Nyquist.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

Figure 1: The most basic digital signal generator is built with a simple binary counter. Its output sequentially addresses the rows of a memory, which holds the successive points of the output signal. It is then converted to an analog signal and filtered.

This design works, but it is not too flexible. If you want to change the output frequency, you need to change the clock frequency, which is not easy to do, especially if you need a fine resolution.

The direct digital synthesizer (DDS) architecture is an improvement on this original design (see Figure 2). Rather than add one to the table look-up address counter at each clock pulse like the counter did in the previous example, a DDS uses an N-bit long-phase register and adds a fixed-phase increment (W) at each clock pulse to this register.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

Figure 2: The basic architecture of a DDS is a variant of the counter-based digital generator, but it allows a fine frequency resolution thanks to a phase register and a binary adder. The key point is that the increment is not necessarily a divider of the phase register maximum value.

N can be quite high (e.g., 32 or 48 bits), so only the most significant bits of the phase register are used to select a value from the phase-to-amplitude look-up table, which is usually nothing more than a ROM preprogrammed with a sine waveform. Assume that you are using the P most significant bits as an address. Then the output of the lookup table is routed to a DAC. And, of course, the analog signal finally goes through a low-pass filter, which is called a “reconstruction filter.” You will understand why in a minute.

How does it work? If the phase increment W is set to one, you will need 2N clock pulses to go through all of the values of the look-up table. One sine period will be generated on the FOUT output each 2N clock pulses, exactly like the aforementioned counter-based architecture. If W is 2, it will be twice as fast and the output frequency will be doubled. As you know, you need a little more than two samples per period to be able to reconstruct a sine signal, so the maximum value of W is 2N–1 – 1. The formula giving the output frequency based on the phase increment is then:DDS-EEtip-122-eq1

Don’t be confused. It is not a simple programmable divider because the phase register doesn’t loop back to the same value after each generated period. The table in Figure 3 may help you understand it.

Figure 3: his spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

Figure 3: This spreadsheet simulation shows the “phase wheel” concept. A fixed angle is added to the phase register at each clock pulse. Note that each period of the output signal is not identical to the previous ones because the phase doesn’t go back to the same value after a full turn.

What make a DDS a fantastic building block are the numeric examples. Just take a standard, low-performance DDS with a phase register of N = 32 bits and a reference clock FCLOCK = 20 MHz. Your DDS can then generate any frequency from DC to nearly 10 MHz with a resolution of the following:DDS-EEtip-122-eq2

Not bad. In fact, the maximum frequency will be a little lower due to constraints on the low-pass filter.—Robert Lacoste, “Direct Digital Synthesis 101,” Circuit Cellar 217, 2008. The issue is available in the CC Webshop.