Amplifier Classes from A to H

Engineers and audiophiles have one thing in common when it comes to amplifiers. They want a design that provides a strong balance between performance, efficiency, and cost.

If you are an engineer interested in choosing or designing the amplifier best suited to your needs, you’ll find columnist Robert Lacoste’s article in Circuit Cellar’s December issue helpful. His article provides a comprehensive look at the characteristics, strengths, and weaknesses of different amplifier classes so you can select the best one for your application.

The article, logically enough, proceeds from Class A through Class H (but only touches on the more nebulous Class T, which appears to be a developer’s custom-made creation).

“Theory is easy, but difficulties arise when you actually want to design a real-world amplifier,” Lacoste says. “What are your particular choices for its final amplifying stage?”

The following article excerpts, in part, answer  that question. (For fuller guidance, download Circuit Cellar’s December issue.)

CLASS A
The first and simplest solution would be to use a single transistor in linear mode (see Figure 1)… Basically the transistor must be biased to have a collector voltage close to VCC /2 when no signal is applied on the input. This enables the output signal to swing

Figure 1—A Class-A amplifier can be built around a simple transistor. The transistor must be biased in so it stays in the linear operating region (i.e., the transistor is always conducting).

Figure 1—A Class-A amplifier can be built around a simple transistor. The transistor must be biased in so it stays in the linear operating region (i.e., the transistor is always conducting).

either above or below this quiescent voltage depending on the input voltage polarity….

This solution’s advantages are numerous: simplicity, no need for a bipolar power supply, and excellent linearity as long as the output voltage doesn’t come too close to the power rails. This solution is considered as the perfect reference for audio applications. But there is a serious downside.

Because a continuous current flows through its collector, even without an input signal’s presence, this implies poor efficiency. In fact, a basic Class-A amplifier’s efficiency is barely more than 30%…

CLASS B
How can you improve an amplifier’s efficiency? You want to avoid a continuous current flowing in the output transistors as much as possible.

Class-B amplifiers use a pair of complementary transistors in a push-pull configuration (see Figure 2). The transistors are biased in such a way that one of the transistors conducts when the input signal is positive and the other conducts when it is negative. Both transistors never conduct at the same time, so there are very few losses. The current always goes to the load…

A Class-B amplifier has more improved efficiency compared to a Class-A amplifier. This is great, but there is a downside, right? The answer is unfortunately yes.
The downside is called crossover distortion…

Figure 2—Class-B amplifiers are usually built around a pair of complementary transistors (at left). Each transistor  conducts 50% of the time. This minimizes power losses, but at the expense of the crossover distortion at each zero crossing (at right).

Figure 2—Class-B amplifiers are usually built around a pair of complementary transistors (at left). Each transistor conducts 50% of the time. This minimizes power losses, but at the expense of the crossover distortion at each zero crossing.

CLASS AB
As its name indicates, Class-AB amplifiers are midway between Class A and Class B. Have a look at the Class-B schematic shown in Figure 2. If you slightly change the transistor’s biasing, it will enable a small current to continuously flow through the transistors when no input is present. This current is not as high as what’s needed for a Class-A amplifier. However, this current would ensure that there will be a small overall current, around zero crossing.

Only one transistor conducts when the input signal has a high enough voltage (positive or negative), but both will conduct around 0 V. Therefore, a Class-AB amplifier’s efficiency is better than a Class-A amplifier but worse than a Class-B amplifier. Moreover, a Class-AB amplifier’s linearity is better than a Class-B amplifier but not as good as a Class-A amplifier.

These characteristics make Class-AB amplifiers a good choice for most low-cost designs…

CLASS C
There isn’t any Class-C audio amplifier Why? This is because a Class-C amplifier is highly nonlinear. How can it be of any use?

An RF signal is composed of a high-frequency carrier with some modulation. The resulting signal is often quite narrow in terms of frequency range. Moreover, a large class of RF modulations doesn’t modify the carrier signal’s amplitude.

For example, with a frequency or a phase modulation, the carrier peak-to-peak voltage is always stable. In such a case, it is possible to use a nonlinear amplifier and a simple band-pass filter to recover the signal!

A Class-C amplifier can have good efficiency as there are no lossy resistors anywhere. It goes up to 60% or even 70%, which is good for high-frequency designs. Moreover, only one transistor is required, which is a key cost reduction when using expensive RF transistors. So there is a high probability that your garage door remote control is equipped with a Class-C RF amplifier.

CLASS D
Class D is currently the best solution for any low-cost, high-power, low-frequency amplifier—particularly for audio applications. Figure 5 shows its simple concept.
First, a PWM encoder is used to convert the input signal from analog to a one-bit digital format. This could be easily accomplished with a sawtooth generator and a voltage comparator as shown in Figure 3.

This section’s output is a digital signal with a duty cycle proportional to the input’s voltage. If the input signal comes from a digital source (e.g., a CD player, a digital radio, a computer audio board, etc.) then there is no need to use an analog signal anywhere. In that case, the PWM signal can be directly generated in the digital domain, avoiding any quality loss….

As you may have guessed, Class-D amplifiers aren’t free from difficulties. First, as for any sampling architecture, the PWM frequency must be significantly higher than the input signal’s highest frequency to avoid aliasing….The second concern with Class-D amplifiers is related to electromagnetic compatibility (EMC)…

Figure 3—A Class-D amplifier is a type of digital amplifier (at left). The comparator’s output is a PWM signal, which is amplified by a pair of low-loss digital switches. All the magic happens in the output filter (at right).

Figure 3—A Class-D amplifier is a type of digital amplifier. The comparator’s output is a PWM signal, which is amplified by a pair of low-loss digital switches. All the magic happens in the output filter.

CLASS E and F
Remember that Class C is devoted to RF amplifiers, using a transistor conducting only during a part of the signal period and a filter. Class E is an improvement to this scheme, enabling even greater efficiencies up to 80% to 90%. How?
Remember that with a Class-C amplifier, the losses only occur in the output transistor. This is because the other parts are capacitors and inductors, which theoretically do not dissipate any power.

Because power is voltage multiplied by current, the power dissipated in the transistor would be null if either the voltage or the current was null. This is what Class-E amplifiers try to do: ensure that the output transistor never has a simultaneously high voltage across its terminals and a high current going through it….

CLASS G AND CLASS H
Class G and Class H are quests for improved efficiency over the classic Class-AB amplifier. Both work on the power supply section. The idea is simple. For high-output power, a high-voltage power supply is needed. For low-power, this high voltage implies higher losses in the output stage.

What about reducing the supply voltage when the required output power is low enough? This scheme is clever, especially for audio applications. Most of the time, music requires only a couple of watts even if far more power is needed during the fortissimo. I agree this may not be the case for some teenagers’ music, but this is the concept.

Class G achieves this improvement by using more than one stable power rail, usually two. Figure 4 shows you the concept.

Figure 4—A Class-G amplifier uses two pairs of power supply rails. b—One supply rail is used when the output signal has a low power (blue). The other supply rail enters into action for high powers (red). Distortion could appear at the crossover.

Figure 4—A Class-G amplifier uses two pairs of power supply rails. b—One supply rail is used when the output signal has a low power (blue). The other supply rail enters into action for high powers (red). Distortion could appear at the crossover.

The Future of Nanotube Computing

For decades, silicon-based transistors have been the workhorse of the semiconductor industry, achieving remarkable advances in computational power. While advances continue to be made, alternative technologies are being explored to increase computational power and efficiency beyond the limits of silicon.

Carbon nanotubes (CNTs) are nanocylinders of carbon atoms, approximately 1 nm in diameter. They have amazing electrical, thermal, and physical properties. CNTs can be used to form CNT field-effect transistors (CNFETs), which use CNTs as the channel material of the transistor, with traditional lithographically defined sources, drains, and gates. It has been projected that digital systems made from carbon nanotubes can achieve more than an order of magnitude benefit in energy delay product (a common metric to compare a circuit’s performance and energy efficiency) compared to competing technologies.

However, it has been impracticable to realize these system-level benefits due to the inability to manufacture CNT-based circuits. This limitation stems from substantial imperfections inherent with the CNTs, including mispositioned and metallic CNTs. Mispositioned CNTs cause erroneous connections in a circuit, metallic (rather than semiconducting) CNTs decrease Ion/Ioff ratio, both potentially resulting in incorrect logic functionality and power wastage.

The trivial solution to these obstacles is to grow 100% perfectly aligned and semiconducting CNTs. However, this is currently infeasible, and likely never will be. Thus, to overcome these inherent imperfections, our Stanford University research team uses the imperfection-immune design paradigm. This paradigm combines processing solutions and design “tricks” to overcome these imperfections in the very-large-scale integration (VLSI) compatible manner.

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo: Norbert von der Groeben )

Max Shulaker, a graduate student at Stanford University and author of this essay, holds a wafer filled with CNTs. (Photo credit: Norbert von der Groeben )

We begin by growing the CNTs highly aligned. This is accomplished by growing the CNTs on a crystalline quartz substrate. The CNTs grow along the crystalline boundary of the quartz and result in highly aligned growths—99.5% alignment. However, for VLSI applications, there are millions or billions of transistors, resulting in billions of CNTs. Thus 99.5% is insufficient.

In addition, we employ mispositioned CNT immune design, which is a technique that renders the circuits that we make 100% immune to any mispositioned CNTs that would be left on the wafer. An important point is that the design is not dependent on the exact placement of the individual CNTs. It works for any arbitrary configuration of CNTs, and thus is manufacturable and scalable to very-large-scale circuits.

To remove metallic CNTs, we break them down, much like a fuse. We turn off all semiconducting CNTs in the circuit and pulse a large voltage across the transistors. Only the metallic CNTs conduct current, and by passing enough current, eventually heat up to

Max M. Shulaker, who holds a wafer filled with carbon nanotubes (CNTs), is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

Max M. Shulaker, who wrote this essay for Circuit Cellar, holds a wafer filled with carbon nanotubes (CNTs). Max is a PhD candidate at Stanford University where he earned his BS in Electrical Engineering. He is part of a Stanford research team that recently built the first functioning computer using CNTs. Max works on experimentally demonstrating nanosystems with emerging technologies. His current research focuses on realizing increased levels of integration for CNT-based digital logic circuits. (Photo credit: Norbert von der Groeben)

the point where they break down, much like a fuse. The trick is being able to perform this breakdown at a chip  scale. Computers today have billions of transistors. It would be infeasible to breakdown each transistor one by one. VLSI-compatible metallic CNT removal (VMR) is a design technique that enables the breakdown to be performed at an entire chip scale.

The imperfection-immune design paradigm, coupled with CNT-specific fabrication processing resulting in high-yield devices, permits, for the first time, the realization of larger-scale digital systems using this very promising technology. Most recently, a basic computer was fabricated at Stanford University completely using CNFETs. The CNT computer was composed of tens of thousands of CNTs, demonstrating the ability to manufacture CNT circuits in a scalable, and thus manufacturable, manner. The computer executes the subtract and branch if negative (SUBNEG) instruction, which is Turing complete, adding to the computer’s generality. As a demonstration, the CNT computer concurrently counted integers and sorted integers, continuously swapping between the two processes. To demonstrate the computer’s flexibility, it also emulated 20 different instructions from the commercial MIPS instruction set.

The CNT computer, culminating years of work by a team of researchers at Stanford University led by Professors Subhasish Mitra and Philip Wong, demonstrates that CNTs are a manufacturable and feasible technology. Beyond CNTs, it is a step forward for the broader field of emerging nanotechnologies. While many alternatives to silicon are being explored, the CNT computer represents an initial demonstration of one of these emerging technologies coming to fruition.

High-Speed Laser Range Finder Board with IMU

Integrated

The NavRanger-OEM

The NavRanger-OEM combines a 20,000 samples per second laser range finder with a nine-axis inertial measurement unit (IMU) on a single 3“ × 6“ (7.7 × 15.3 cm) circuit board. The board features I/O resources and processing capability for application-specific control solutions.

The NavRanger‘s laser range finder measures the time of flight of a short light pulse from an IR laser. The time to digital converter has a 65-ps resolution (i.e., approximately 1 cm). The Class 1M laser has a 10-ns pulse width, a 0.8 mW average power, and a 9° × 25° divergence without optics. The detector comprises an avalanche photo diode with a two-point variable-gain amplifier and variable threshold digitizer. These features enable a 10-cm × 10-cm piece of white paper to be detected at 30 m with a laser collimator and 25-mm receiver optics.

The range finder includes I/O to build a robot or scan a solution. The wide range 9-to-28-V input supply voltage enables operation in 12- and 24-V battery environments. The NavRanger‘s IMU is an InvenSense nine-axis MPU-9150, which combines an accelerometer, a gyroscope, and a magnetometer on one chip. A 32-bit Freescale ColdFire MCF52255 microcontroller provides the processing the power and additional I/O. USB and CAN buses provide the board’s high-speed interfaces. The board also has connectors and power to mount a Digi International XBee wireless module and a TTL GPS.

The board comes with embedded software and a client application that runs on a Windows PC or Mac OS X. It also includes modifiable source code for the embedded and client applications. The NavRanger-OEM costs $495.

Integrated Knowledge Systems, Inc.
www.iknowsystems.com

2.4-GHz RF High-Power Amplifier

Microchip

The SST12CP12 high-power amplifier

The SST12CP12 is a 2.4-GHz RF high-power amplifier that adds support for 256-QAM ultra-high data rate modulation. With its high linear output power, this amplifier significantly extends the range of IEEE 802.11b/g/n WLAN systems while providing excellent power at the maximum 256-QAM data rate. The amplifier is also spectrum-mask compliant up to 28.5 dBm for 802.11b/g communication and utilizes orthogonal frequency-division multiplexing (OFDM) to correct severe channel conditions without using complex equalization filters.

The SST12CP12 power amplifier has a 380mA at 23 dBm low operating current, which enables more transmission channels and a higher data rate for each system. The amplifier also features easy to use 50-Ω on-chip input match and simple output match. In addition, the integrated linear power detector provides temperature stability and immunity to voltage standing wave ratio (VSWR) radio-wave reflection to provide accurate output power control.

The SST12CP12 costs $0.97 each, in 10,000-unit quantities. It ships in a 3-mm × 3-mm × 0.55-mm, 16-pin QFN package.

Microchip Technology, Inc.
www.microchip.com

Brian Shewan Wins the CC Code Challenge (Week 27)

We have a winner of last week’s CC Weekly Code Challenge, sponsored by IAR Systems! We posted a code snippet with an error and challenged the engineering community to find the mistake!

Congratulations to Brian Shewan of Nova Scotia, Canadafor winning the CC Weekly Code Challenge for Week 27! Brian will receive Circuit Cellar 2011 and 2012 Archive CD.

Brian’s correct answer was randomly selected from the pool of responses that correctly identified an error in the code. Brian answered:

Line 22: Shift register won’t shift. Change to “ShiftReg_ClkB <= {ShiftReg_ClkB[1:0], clkA_Change}”

2013_code_challenge_27_answer

You can see the complete list of weekly winners and code challenges here.

What is the CC Weekly Code Challenge?
Each week, Circuit Cellar’s technical editors purposely insert an error in a snippet of code. It could be a semantic error, a syntax error, a design error, a spelling error, or another bug the editors slip in. You are challenged to find the error.Once the submission deadline passes, Circuit Cellar will randomly select one winner from the group of respondents who submit the correct answer.

Inspired? Want to try this week’s challenge? Get started!

Submission Deadline: The deadline for each week’s challenge is Sunday, 12 PM EST. Refer to the Rules, Terms & Conditions for information about eligibility and prizes.

Turn Your Android Device into an Application Tool

A few years ago, the Android Open Accessory initiative was announced with the aim of making it easier for hardware manufacturers to create accessories that work with every Android device. Future Technology Devices International (FTDI) joined the initiative and last year introduced the FTD311D multi-interface Android host IC. The goal was to enable engineers and designers to make effective use of tablets and smartphones with the Android OS, according to Circuit Cellar columnist Jeff Bachiochi.

The FTD311D “provides an instant bridge from an Android USB port(B) to peripheral hardware over general purpose input-out (GPIO), UART, PWM, I2C Master, SPI Slave, or SPI Master interfaces,” Bachiochi says.

In the magazine’s December issue Bachiochi takes a comprehensive look at the USB Android host IC and how it works. By the end of his article, readers will have learned quite a bit about how to use FTDI’s apps and the FT311D chip to turn an Android device into their own I/0 tool.

Bachiochi used the SPI Master demo to read key presses and set LED states on this SPI slave 16-key touch panel.

Bachiochi used the SPI Master demo to read key presses and set LED states on this SPI slave 16-key touch panel.

Here is how Bachiochi describes the FT311D and its advantages:

The FT311D is a full-speed USB host targeted at providing access to peripheral hardware from a USB port on an Android device. While an Android device can be a USB host, many are mobile devices with limited power. For now, these On-The-Go (OTG) ports will be USB devices only (i.e., they can only connect to a USB host as a USB device).

Since the USB host is responsible for supplying power to a USB peripheral device, it would be bad design practice to enable a USB peripheral to drain an Android mobile device’s energy. Consequently, the FT311D takes on the task of USB host, eliminating any draw on the Android device’s battery.

All Android devices from V3.1 (Honeycomb) support the Android Open Accessory Mode (AOAM). The AOAM is the complete reverse of the conventional USB interconnect. This game-changing approach to attaching peripherals enables three key advantages. First, there is no need to develop special drivers for the hardware; second, it is unnecessary to root devices to alter permissions for loading drivers; and third, the peripheral provides the power to use the port, which ensures the mobile device battery is not quickly drained by the external hardware being attached.

Since the FT311D handles the entire USB host protocol, USB-specific firmware programming isn’t required. As the host, the FT311D must inquire whether the connected device supports the AOAM. If so, it will operate as an Open Accessory Mode device with one USB BULK IN endpoint and one USB BULK OUT endpoint (as well as the control endpoint.) This interface will be a full-speed (12-Mbps) USB enabling data transfer in and out.

The AOAM USB host has a set of string descriptors the Android OS is capable of reading. These strings are (user) associated with an Android OS application. The Android then uses these strings to automatically start the application when the hardware is connected. The FT311D is configured for one of its multiple interfaces via configuration inputs at power-up. Each configuration will supply the Android device with a unique set of string descriptors, therefore enabling different applications to run, depending on its setup.

The FT311D’s configuration determines whether each application will have access to several user interface APIs that are specific to each configuration.

The article goes on to examine the various interfaces in detail and to describe a number of demo projects, including a multimeter.

Many of Bachiochi's projects use printable ASCII text commands and replies. This enables a serial terminal to become a handy user I/O device. This current probe circuit outputs its measurements in ASCII-printable text.

Many of Bachiochi’s projects use printable ASCII text commands and replies. This enables a serial terminal to become a handy user I/O device. This current probe circuit outputs its measurements in ASCII-printable text.

Multimeters are great tools. They have portability that enables them to be brought to wherever a measurement must be made. An Android device has this same ability. Since applications can be written for these devices, they make a great portable application tool. Until the AOAM’s release, there was no way for these devices to be connected to any external circuitry and used as an effective tool.

I think FTDI has bridged this gap nicely. It provided a great interface chip that can be added to any circuit that will enable an Android device to serve as an effective user I/O device. I’ve used the chip to quickly interface with some technology to discover its potential or just test its abilities. But I’m sure you are already thinking about the other potential uses for this connection.

Bachiochi is curious to hear from readers about their own ideas.

If you think the AOAM has future potential, but you want to know what’s involved with writing Android applications for a specific purpose, send me an e-mail and I’ll add this to my list of future projects!

You can e-mail Bachiochi at jeff.bachiochi@imaginethatnow.com or post your comment here.

 

Kang Usman Wins the CC Code Challenge (Week 26)

We have a winner of last week’s CC Weekly Code Challenge, sponsored by IAR Systems! We posted a code snippet with an error and challenged the engineering community to find the mistake!

Congratulations to Kang Usman of Jakarta, Indonesia for winning the CC Weekly Code Challenge for Week 26! Kang will receive an IAR Kickstart: KSK-FM3-48PMC-USB.

Kang’s correct answer was randomly selected from the pool of responses that correctly identified an error in the code. Kang answered:

Line 46: need [ and ]. it should be translate([0,0,2*ThreadThick])

2013_code_challenge_26_answer

You can see the complete list of weekly winners and code challenges here.

What is the CC Weekly Code Challenge?
Each week, Circuit Cellar’s technical editors purposely insert an error in a snippet of code. It could be a semantic error, a syntax error, a design error, a spelling error, or another bug the editors slip in. You are challenged to find the error.Once the submission deadline passes, Circuit Cellar will randomly select one winner from the group of respondents who submit the correct answer.

Inspired? Want to try this week’s challenge? Get started!

Submission Deadline: The deadline for each week’s challenge is Sunday, 12 PM EST. Refer to the Rules, Terms & Conditions for information about eligibility and prizes.

NPU Blade for High-Throughput Packet Processing

ADLINK

The aTCA-N700 NPU blade

The aTCA-N700 Advanced Telecommunications Computing Architecture (ATCA) packet processing blade features dual 32-core network processing units (NPUs) for parallel processing and up to 320G switching capability. The blade delivers advanced packet and security processing capabilities for high-performance, high-throughput, low-latency applications in broadband infrastructure elements (e.g., wireless access point controllers, network security platforms, deep packet inspection, IPTV, LTE gateways, and media servers).

The ADLINK aTCA-N700 complies with the ATCA Base Specification (PICMG 3.0 R.3.0) and the ATCA Ethernet Specification (PICMG 3.1 R2.0). It is powered by dual Cavium OCTEON II CN6880 processors, which each have 32 cnMIPS64 V2 cores and a highly optimized architecture for deep packet inspection, network security, and traffic-shaping applications.

Eight memory sockets are provided to support VLP DDR3-1333 REG/ECC up to 128 GB and data transfer bandwidth up to 320 Gbps. The aTCA-N700 blade also supports TCAM for fast router lookup. The blade features a powerful local management processor (LMP) and a quad-core Freescale Semiconductor QorIQ P2041, which makes local management more flexible and convenient and enables the Cavium processors to focus on packet processing.

Each set of NPUs features its own NOR boot flash memory and NAND OS flash memory in a redundant configuration. The LMP has two EEROM for U-Boot image storage and two SSD devices for operating system and application image storage.

For Ethernet connectivity, the aTCA-N700 utilizes the high-performance Broadcom BCM 56842 Ethernet switch to connect the CN6880 packet processors, backplanes, and I/O ports with the switch fabric providing up to 320 Gbps bandwidth. The aTCA-N700 uses dual fabric interface channels and two base interfaces for data transfer.

Contact ADLINK for pricing.

ADLINK Technology, Inc.
www.adlinktech.com

Arduino Uno Blueprint — Free Download

Elektor.Labs recently produced an Arduino Uno blueprint poster for element14. The poster details everything you need to know about the Arduino Uno.

Download it for free here.

Download your Arduino Uno poster

Download your Arduino Uno poster

The poster also includes coding notes that will get you working with your Arduino Uno in no time.

About the Arduino Uno:

  • Core Architecture: AVR
  • Core Sub-Architecture: megaAVR
  • Silicon Core: ATmega328
  • Features: The Arduino Uno is powered via USB or an external supply. It’s programmed with Arduino software.

Recent Arduino-related articles from Circuit Cellar:

 

6DoF Robotic Arm

GlobalSpecialties

The R680 Banshi Robotic Arm

The R680 Banshi Robotic Arm is an affordable robot designed for educators and hobbyists. It can help users learn the basics of electronics, mechanics, and programming. The Banshi is controlled by an ATmega64 microcontroller that is programmable via open-source tools in C.

The robot includes many example programs that can be easily downloaded to the robot using the supplied USB interface and the RobotLoader software. You can also use the free open-source WinAVR software to write your own custom programs.

The robot can be controlled with the included keyboard or RACS software. The software can record and play back the Banshi’s movements. You can use I/Os and the flexible I2C bus system to add extra modules that enable the robot to react to its environment.

GlobalSpecialties-kit

The Banshi Robot kit

The Banshi Robot comes unassembled as a kit with included assembly tools. The robot’s additional features include six degrees of freedom (6DoF), a 12-V power supply, an I2C bus, a USB interface, and a complete 72-page manual.

The Banshi Robotic Arm costs $199.

Global Specialties
http://globalspecialties.com

Registration to Attend the 2014 Design and Verification Conference

Registration to attend the 2014 Design and Verification Conference (DVCon) opens December 6, 2013. The conference will be held March 3-6, 2014, at the DoubleTree Hotel in San Jose, California.

DVCon is a premier conference for the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits, according to the website dvcon.org. DVCon primarily focuses on the practical use of specialized design and verification languages such as SystemC,  SystemVerilog and e, assertions in SVA or PSL, as well as the use of AMS languages, design automation using IP-XACT,  and the  use of general-purpose languages C and C++.

Conference attendees are generally designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools.  The 2013 conference drew a record turnout. Overall attendance rose to 883, including full conference and exhibit only registration.

If you are interested in attending the conference,  becoming a DVCon exhibitor, or obtaining more information about DVCon, please visit the conference website.  

DVCon is sponsored by Accellera Systems Initiative, an independent, nonprofit industry consortium dedicated to the development and standardization of design and verification languages. The organization accelerates standards development, and as part of its ongoing partnership with the Institute of Electrical and Electronics Engineers (IEEE), its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control.

Emerging Memory Technologies

Some experts predict it will be at least another decade before new memory technologies offer the low prices and wide availability to compete with NAND-based flash memory. Nonetheless, it’s worthwhile to look at potential NAND-flash successors, including phase-change RAM (PRAM), resistive RAM (ReRAM), and magnetoresistive RAM (MRAM).

In December’s Circuit Cellar magazine, now available online, Faiz Rahman describes and compares the newest memory technologies available for embedded systems.

“I cover only those devices that are now commercially available, but bear in mind that many other technologies are being hotly pursued in academic and corporate research labs worldwide,” says Rahman, an Ohio University visiting professor who received his PhD in Electrical Engineering from Imperial College, London.

For example, last summer MIT Technology Review reported on a startup company’s testing of crossbar memory. The new technology, according to an August 14, 2013, article written by Tom Simonite, can store data 40 times as densely as the most compact memory available and is faster and more energy-efficient.

Here are the commercially-available technologies Rahman considers and some of his insights. (For the full article with more details, including an update on manufacturers of the latest memory devices, check out the December issue.)

PHASE-CHANGE RAM
One of the most interesting memory types to emerge in recent years is one that stores data as order or disorder in small islands of a special material. The structural transition

The structure of phase-change RAM cells in reset and set states is shown.

The structure of phase-change RAM cells in reset and set states is shown.

between ordered and disordered phases is driven by controlled heating of the material island…

There have been several recent advances in phase-change RAM (PRAM) technology. Perhaps the most remarkable is the ability to control the cell-heating current precisely enough to create several intermediate cell-resistance values. This immediately increases the memory capacity as each cell can be made to store more than one bit. For example, if eight resistance values can be created and distinguished, then the cell can be used to store three bits, thus tripling the memory capacity. This is now a routinely used technique implemented with PRAM devices.

MAGNETORESISTIVE RAM
We have all wished for a computer with no start-up delay that could be ready to use almost as soon as it was powered up. Such a computer will need to use an inexpensive

A spin-torque magnetoresistive RAM cell’s structure includes a free layer, a tunnel barrier, and a fixed layer.

A spin-torque magnetoresistive RAM cell’s structure includes a free layer, a tunnel barrier, and a fixed layer.

but fast nonvolatile memory. This combination is difficult to come by, but proponents of magnetoresistive RAM (MRAM) think boot times could soon become outdated as this new memory becomes a mature product….

MRAM’s nonvolatility alone will not make it a potential game-changing technology. Its high-access speed is what makes it special. Unlike other nonvolatile memory (e.g., EEPROMs and flash), MRAM boasts typical access speeds of 35 ns and potentially as short as 4 ns, with further developments. This combined with MRAM’s extremely high endurance and data retention periods of more than 20 years even makes the technology suitable for use as CPU cache memories, which is a very demanding application.

One further advantage of MRAM is that its basic architecture—where the access transistor can be formed directly on top of the magnetic tunnel junction (MTJ)—enables very dense integration, greatly reducing the cost of storage per bit and making MRAM well suited for use in solid-state disks.

FERROELECTRIC RAM
In many ways, DRAM is an example of an ideal memory, if it weren’t for its volatility… The problem is that the charge stored in a DRAM cell tends to disappear due to self-discharge

A ferroelectric RAM cell’s organizational structure is shown.

A ferroelectric RAM cell’s organizational structure is shown.

after only a few milliseconds. This means that all DRAM chips have to be periodically read and every cell’s state must be restored every few milliseconds. The requirement for periodic “refresh” operations increases the power consumption of DRAM banks, in addition to endangering data integrity in the case of even short power supply dips.

Within this backdrop, ferroelectric RAM (FRAM) became a potential game changer when it was introduced in the early 1990s…The permanence of induced electrical polarization in ferroelectric capacitors endows FRAMs with their nonvolatility. To write a particular bit, a FRAM’s cell capacitor is briefly charged in one direction to polarize the ferroelectric material between its plates. The capacitor voltage can then be removed and the bit state will be retained in the directional sense of the dielectric material’s polarization. No charges may leak away, and the polarization can be maintained for many years making FRAM, in a sense, a nonvolatile analog of DRAM….

A big advantage of using FRAM in microcontrollers is that just one memory can be used for program, data, and information storage instead of having to use separate flash, SRAM, and EEPROM blocks, which has been the trend so far.

RESISTIVE RAM
Phase-change memory uses programmed heat-generating current pulses to affect memory cell resistance changes. However, resistive RAM (ReRAM)—a still developing memory breed—uses voltage pulses to make resistance changes. This memory technology

A typical resistive RAM cell’s structure is shown.

A typical resistive RAM cell’s structure is shown.

utilizes materials and structures where suitable voltages can alter memory cells’ resistive states so they can store one or more data bits, similar to PRAM.

There are strong hints that ReRAM is capable of very fast switching with symmetric read and write times of less than 10 ns. This comes with a remarkably low power consumption, which should make this technology ideal for many applications.

As if these attributes were not enough, ReRAM cells are very small and can be placed extremely close together, which results in high-density memory fabrics.

Rahman’s article also introduces manufacturers offering products with the latest memory technologies, but he declares no single memory device the best. Despite manufacturers extolling their particular products, those that succeed will need to be available in high volume and at low cost, he says. They also must offer high-storage densities, he says, a bar most new memory technologies struggle to reach.