C-Programmable Robot Kit

ASURO Robot

ASURO Robot

Global Specialties recently introduced the ASURO Robot, a small autonomous multi-sensored robot developed for educational purposes by the DLR, the German Aerospace Center.

The  ASURO is completely programmable in C. Except for the printed circuit boards (PCB), only standard parts are utilized and freeware tools can be used for programming. The ASURO comes unassembled and includes a soldering guide, making it suitable as an introduction into processor-controlled hobby electronics for school, university, and technical education projects.

The ASURO Robot’s features include an ATmega8L microcontroller; an 8-bit AVR-RISC processor; a software and training manual CD; AVR-GCC freeware for use with Windows or Linux; a USB IR transceiver with flash software; remote control and PC-programming possibilities via USB transceiver; wireless control possibilities with optional Bluetooth and 433 MHz RF; six collision-detector sensors; an optical line-tracker unit; two independently controlled 3V-DC motors; an odometer sensor on both wheels; and pre-programmed firmware for easy hardware testing.

The list price is $99.

Global Specialties
 

Issue 278: EQ Answers

Problem 1—Tom, an FPGA designer, is helping out on a system that handles standard-definition digital video at 27 MHz and stores it into an SDRAM that runs at 200 MHz. He discovered the following logic in the FPGA (see Figure 1).

Let’s see if we can work out what it does. To start with, what is the output of the XOR gate in?

Answer 1—When the 27-MHz clock goes from low to high, the first flip-flop changes state. Let’s say that its output goes from low to high as well. Then, when the clock goes from high to low, the second flip-flop’s output will become the same as the first.

On the clock’s next rising edge, the first flip-flop will change again, this time from high to low. And on the next falling edge, the second one will follow suit.

Putting it another way, following each rising edge of the clock, the two flip-flops are different. Following each falling edge, they’re the same. Since we’re feeding them into an XOR gate, the gate’s output will be high following the clock’s rising edge and low following the falling edge. In other words, the XOR gate’s is a replica of the clock signal itself!

Problem 2—Why is this necessary?

Answer 2—In many FPGA architectures, clock signals are automatically assigned to special clock routing resources, which are different from—and kept separate from—the routing resources used for “ordinary” signals. The tools actually discourage (or even prevent) you from using a clock as an input to a gate or to any input of a flip-flop other than the clock input.

Therefore, when you need to pass a clock into another timing domain as a signal, it becomes necessary to generate an ordinary signal that is a replica of the clock. This is one way to accomplish that.

Problem 3—What is the AND gate’s output?

Answer 3—The three flip-flops in the 200-MHz domain have a delayed versions of the (replica) 27-MHz clock signal. The first two function as a conventional synchronizer to minimize the effects of metastability. The third one, along with the AND gate, functions as an edge detector, generating a one-clock pulse in the 200-MHz clock domain following each rising edge of the 27-MHz clock. This pulse might be used, for example, to initiate a write request in the SDRAM for each video data word.

Problem 4—Tom decided to verify the circuit’s operation in his logic simulator, but immediately ran into a problem. What was the problem and what could be added to the circuit to make simulation possible?

Answer 4—There is a subtle problem here for a simulator: All of the flip-flops start out in the “unknown” state. Feeding that back (inverted) to the first flip-flop leaves it in an unknown state. The entire simulation will never get out of the unknown state, even though we can reason that it doesn’t matter which actual state the first flip-flop starts out in. The XOR gate’s output will be known after one full clock cycle. To fix this, it is necessary to explicitly reset the first flip-flop at the beginning of the simulation, then the rest of the circuit will simulate normally.

Low-Power Mini-ITX Motherboard

Habey HB131 mini-ITX motherboard.

Habey HB131 mini-ITX motherboard.

The HB131 mini-ITX motherboard is based on the low-power Intel Atom Cedar Trail platform. The small, 170-mm × 170-mm motherboard is high-performance, reliable, secure, and easy to manage. The platform is well-suited for point-of-sale, self-service terminals, queue machines, and digital signage.

The dual-core Atom D2550 processor is offered with Intel’s NM10 chipset. It features lower power consumption and more enhanced graphics than previous Atom processors.

The motherboard is equipped with dual gigabit LAN ports and rich I/O. Additional features include Wake-on-LAN, a 1-to-~255-level watchdog timer, and shared system memory as video memory.

Contact HABEY for pricing.

HABEY USA, Inc.
www.habeyusa.com

CC279: What’s Ahead in the October Issue

Although we’re still in September, it’s not too early to be looking forward to the October issue already available online.

The theme of the issue is signal processing, and contributor Devlin Gualtieri offers an interesting take on that topic.

Gualtieiri, who writes a science and technology blog, looks at how to improve Improvig Microprocessor Audio microprocessor audio.

“We’re immersed in a world of beeps and boops,” Gualtieri says. “Every digital knick-knack we own, from cell phones to microwave ovens, seeks to attract our attention.”

“Many simple microprocessor circuits need to generate one, or several, audio alert signals,” he adds. “The designer usually uses an easily programmed square wave voltage as an output pin that feeds a simple piezoelectric speaker element. It works, but it sounds awful. How can microprocessor audio be improved in some simple ways?”

Gualtieri’s article explains how analog circuitry and sine waves are often a better option than digital circuitry and square waves for audio alert signals.

Another article that touches on signal processing is columnist Colin Flynn’s look at advanced methods of debugging an FPGA design. It’s the debut of his new column Programmable Logic in Practice.

“This first article introduces the use of integrated logic analyzers, which provide an internal view of your running hardware,” O’Flynn says. “My next article will continue this topic and show you how hardware co-simulation enables you to seamlessly split the verification between real hardware interfacing to external devices and simulated hardware on your computer.”

You can find videos and other material that complement Colin’s articles on his website.

Another October issue highlight is a real prize-winner. The issue features the first installment of a two-part series on the SunSeeker Solar Array Tracker, which won third SunSeekerplace in the 2012 DesignSpark chipKit challenge overseen by Circuit Cellar.

The SunSeeker, designed by Canadian Graig Pearen, uses a Microchip Technology chipKIT Max32 and tracks, monitors, and adjusts PV arrays based on weather and sky conditions. It measures PV and air temperature, compiles statistics, and communicates with a local server that enables the SunSeeker to facilitate software algorithm development. Diagnostic software monitors the design’s motors to show both movement and position.

Pearen, semi-retired from the telecommunications industry and a part-time solar technician, is still refining his original design.

“Over the next two to three years of development and field testing, I plan for it to evolve into a full-featured ‘bells-and-whistles’ solar array tracker,” Pearen says. “I added a few enhancements as the software evolved, but I will develop most of the additional features later.”

Walter Krawec, a PhD student studying Computer Science at the Stevens Institute of Technology in Hoboken, NJ, wraps up his two-part series on “Experiments in Developmental Robotics.”

In Part 1, he introduced readers to the basics of artificial neural networks (ANNs) in robots and outlined an architecture for a robot’s evolving neural network, short-term memory system, and simple reflexes and instincts. In Part 2, Krawec discusses the reflex and instinct system that rewards an ENN.

“I’ll also explain the ‘decision path’ system, which rewards/penalizes chains of actions,” he says. “Finally, I’ll describe the experiments we’ve run demonstrating this architecture in a simulated environment.”

Videos of some of Krawec’s robot simulations can be found on his website.

Speaking of robotics, in this issue columnist Jeff Bachiochi introduces readers to the free robot control programming language RobotBASIC and explains how to use it with an integrated simulator for robot communication.

Other columnists also take on a number of very practical subjects. Robert Lacoste explains how inexpensive bipolar junction transistors (BJTs) can be helpful in many designs and outlines how to use one to build an amplifier.

George Novacek, who has found that the cost of battery packs account for half the DIY Battery Chargerpurchase price of his equipment, explains how to build a back-up power source with a lead-acid battery and a charger.

“Building a good battery charger is easy these days because there are many ICs specifically designed for battery chargers,” he says.

Columnist Bob Japenga begins a new series looking at file systems available on Linux for embedded systems.

“Although you could build a Linux system without a file system, most Linux systems will have some sort of file system,” Japenga says. “And there are various types. There are files systems that do not retain their data (volatile) across power outages (i.e., RAM drives). There are nonvolatile read-only file systems that cannot be changed (e.g., CRAMFS). And there are nonvolatile read/write file systems.”

Linux provides all three types of file systems, Japenga says, and his series will address all of them.

Finally, the magazine offers some special features, including an interview with Alenka Zajić, who teaches signal processing and electromagnetics at Georgia Institute of Technology’s School of Electrical and Computer Engineering. Also, two North Carolina State University researchers write about advances in 3-D liquid metal printing and possible applications such as electrical wires that can “heal” themselves after being severed.

For more, check out the Circuit Cellar’s October issue.

 

 

CC279: A Fresh Focus on Programmable Logic

We’re not finished adding new features to our magazine. Last month, we rolled out our redesign and told you a bit about Ayse K. Coskun, who is writing a new bimonthly Green Computing column. This month, we introduce you to columnist Colin O’Flynn.

Colin’s bimonthly column, Programmable Logic in Practice, debuts in this issue. His first article focuses on integrated logic analyzer tools and methods of debugging your FPGA designs (p. 46).

Future articles will continue to feature “advanced information about FPGAs,” Colin says. “I will cover topics including debugging tools, high-level synthesis, high-speed serial interfaces, hard-core processors, interfacing to memory, and so forth.

“To keep this column practical, I’m going to focus on real hardware and tools you will be using. When it comes to programmable logic, there is always a choice of vendors—and I don’t work for any of them.”

Colin is definitely “multimedia.” To help readers better understand each article’s topic, he has set up a companion website, ProgrammableLogicInPractice.com. He wants to avoid too many step-by-step instructions in print. Instead, such steps will be posted on the website, along with example project files and videos, where applicable.

Many Circuit Cellar readers are already familiar with Colin. Since 2002, we have published five articles from this Canadian electrical engineer, who is also a product developer and a lecturer at Dalhousie University in Halifax, NS. Colin earned his master’s degree in applied science from Dalhousie and has also pursued graduate studies in cryptographic systems.
The topics he is pondering for future articles include circuit board layout for high-speed FPGAs, different methods of configuring an FPGA, designing memory into FPGA circuits, and use of vendor-provided and open-source soft-core microcontrollers.

Any designer or engineer interested in programmable logic technologies should check out Colin’s column in this and future issues.

Mary Wilsoneditor@circuitcellar.com